diff mbox series

[02/23] arm: [MVE intrinsics] factorize vqrshlq vrshlq

Message ID 20230505083930.101210-2-christophe.lyon@arm.com
State Accepted
Headers
Series [01/23] arm: [MVE intrinsics] add binary_round_lshift shape |

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Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Christophe Lyon May 5, 2023, 8:39 a.m. UTC 
  Factorize vqrshlq, vrshlq so that they use the same pattern.

2022-09-08  Christophe Lyon <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (MVE_RSHIFT_M_N, MVE_RSHIFT_N): New.
	(mve_insn): Add vqrshl, vrshl.
	* config/arm/mve.md (mve_vqrshlq_n_<supf><mode>)
	(mve_vrshlq_n_<supf><mode>): Merge into ...
	(@mve_<mve_insn>q_n_<supf><mode>): ... this.
	(mve_vqrshlq_m_n_<supf><mode>, mve_vrshlq_m_n_<supf><mode>): Merge
	into ...
	(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
---
 gcc/config/arm/iterators.md | 14 +++++++++++
 gcc/config/arm/mve.md       | 49 ++++++++-----------------------------
 2 files changed, 24 insertions(+), 39 deletions(-)

Comments

Kyrylo Tkachov May 5, 2023, 9:58 a.m. UTC | #1 
> -----Original Message-----
> From: Christophe Lyon <christophe.lyon@arm.com>
> Sent: Friday, May 5, 2023 9:39 AM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>;
> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
> <Richard.Sandiford@arm.com>
> Cc: Christophe Lyon <Christophe.Lyon@arm.com>
> Subject: [PATCH 02/23] arm: [MVE intrinsics] factorize vqrshlq vrshlq
> 
> Factorize vqrshlq, vrshlq so that they use the same pattern.

Ok.
Thanks,
Kyrill

> 
> 2022-09-08  Christophe Lyon <christophe.lyon@arm.com>
> 
> 	gcc/
> 	* config/arm/iterators.md (MVE_RSHIFT_M_N, MVE_RSHIFT_N): New.
> 	(mve_insn): Add vqrshl, vrshl.
> 	* config/arm/mve.md (mve_vqrshlq_n_<supf><mode>)
> 	(mve_vrshlq_n_<supf><mode>): Merge into ...
> 	(@mve_<mve_insn>q_n_<supf><mode>): ... this.
> 	(mve_vqrshlq_m_n_<supf><mode>,
> mve_vrshlq_m_n_<supf><mode>): Merge
> 	into ...
> 	(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
> ---
>  gcc/config/arm/iterators.md | 14 +++++++++++
>  gcc/config/arm/mve.md       | 49 ++++++++-----------------------------
>  2 files changed, 24 insertions(+), 39 deletions(-)
> 
> diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
> index 593be83e0be..e7622fe752a 100644
> --- a/gcc/config/arm/iterators.md
> +++ b/gcc/config/arm/iterators.md
> @@ -435,6 +435,16 @@ (define_int_iterator MVE_INT_N_BINARY_LOGIC   [
>  		     VORRQ_N_S VORRQ_N_U
>  		     ])
> 
> +(define_int_iterator MVE_RSHIFT_M_N   [
> +		     VQRSHLQ_M_N_S VQRSHLQ_M_N_U
> +		     VRSHLQ_M_N_S VRSHLQ_M_N_U
> +		     ])
> +
> +(define_int_iterator MVE_RSHIFT_N   [
> +		     VQRSHLQ_N_S VQRSHLQ_N_U
> +		     VRSHLQ_N_S VRSHLQ_N_U
> +		     ])
> +
>  (define_int_iterator MVE_FP_M_BINARY   [
>  		     VADDQ_M_F
>  		     VMULQ_M_F
> @@ -526,7 +536,9 @@ (define_int_attr mve_insn [
>  		 (VQRDMULHQ_M_S "vqrdmulh")
>  		 (VQRDMULHQ_N_S "vqrdmulh")
>  		 (VQRDMULHQ_S "vqrdmulh")
> +		 (VQRSHLQ_M_N_S "vqrshl") (VQRSHLQ_M_N_U "vqrshl")
>  		 (VQRSHLQ_M_S "vqrshl") (VQRSHLQ_M_U "vqrshl")
> +		 (VQRSHLQ_N_S "vqrshl") (VQRSHLQ_N_U "vqrshl")
>  		 (VQRSHLQ_S "vqrshl") (VQRSHLQ_U "vqrshl")
>  		 (VQSHLQ_M_S "vqshl") (VQSHLQ_M_U "vqshl")
>  		 (VQSHLQ_S "vqshl") (VQSHLQ_U "vqshl")
> @@ -538,7 +550,9 @@ (define_int_attr mve_insn [
>  		 (VRHADDQ_S "vrhadd") (VRHADDQ_U "vrhadd")
>  		 (VRMULHQ_M_S "vrmulh") (VRMULHQ_M_U "vrmulh")
>  		 (VRMULHQ_S "vrmulh") (VRMULHQ_U "vrmulh")
> +		 (VRSHLQ_M_N_S "vrshl") (VRSHLQ_M_N_U "vrshl")
>  		 (VRSHLQ_M_S "vrshl") (VRSHLQ_M_U "vrshl")
> +		 (VRSHLQ_N_S "vrshl") (VRSHLQ_N_U "vrshl")
>  		 (VRSHLQ_S "vrshl") (VRSHLQ_U "vrshl")
>  		 (VSHLQ_M_S "vshl") (VSHLQ_M_U "vshl")
>  		 (VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub")
> (VSUBQ_M_N_F "vsub")
> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index 6b88fdb8a7a..0d3343b6e29 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -1373,17 +1373,18 @@ (define_expand "mve_vorrq_u<mode>"
>  )
> 
>  ;;
> -;; [vqrshlq_n_s, vqrshlq_n_u])
> +;; [vqrshlq_n_s, vqrshlq_n_u]
> +;; [vrshlq_n_u, vrshlq_n_s]
>  ;;
> -(define_insn "mve_vqrshlq_n_<supf><mode>"
> +(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
>    [
>     (set (match_operand:MVE_2 0 "s_register_operand" "=w")
>  	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
>  		       (match_operand:SI 2 "s_register_operand" "r")]
> -	 VQRSHLQ_N))
> +	 MVE_RSHIFT_N))
>    ]
>    "TARGET_HAVE_MVE"
> -  "vqrshl.<supf>%#<V_sz_elem>\t%q0, %2"
> +  "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %2"
>    [(set_attr "type" "mve_move")
>  ])
> 
> @@ -1432,21 +1433,6 @@ (define_insn "mve_vqshluq_n_s<mode>"
>    [(set_attr "type" "mve_move")
>  ])
> 
> -;;
> -;; [vrshlq_n_u, vrshlq_n_s])
> -;;
> -(define_insn "mve_vrshlq_n_<supf><mode>"
> -  [
> -   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> -	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> -		       (match_operand:SI 2 "s_register_operand" "r")]
> -	 VRSHLQ_N))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vrshl.<supf>%#<V_sz_elem>\t%q0, %2"
> -  [(set_attr "type" "mve_move")
> -])
> -
>  ;;
>  ;; [vrshrq_n_s, vrshrq_n_u])
>  ;;
> @@ -3098,18 +3084,19 @@ (define_insn "mve_vqrdmlsdhxq_s<mode>"
>  ])
> 
>  ;;
> -;; [vqrshlq_m_n_s, vqrshlq_m_n_u])
> +;; [vqrshlq_m_n_s, vqrshlq_m_n_u]
> +;; [vrshlq_m_n_s, vrshlq_m_n_u]
>  ;;
> -(define_insn "mve_vqrshlq_m_n_<supf><mode>"
> +(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
>    [
>     (set (match_operand:MVE_2 0 "s_register_operand" "=w")
>  	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
>  		       (match_operand:SI 2 "s_register_operand" "r")
>  		       (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -	 VQRSHLQ_M_N))
> +	 MVE_RSHIFT_M_N))
>    ]
>    "TARGET_HAVE_MVE"
> -  "vpst\;vqrshlt.<supf>%#<V_sz_elem>	%q0, %2"
> +  "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %2"
>    [(set_attr "type" "mve_move")
>     (set_attr "length""8")])
> 
> @@ -3145,22 +3132,6 @@ (define_insn "mve_vrev64q_m_<supf><mode>"
>    [(set_attr "type" "mve_move")
>     (set_attr "length""8")])
> 
> -;;
> -;; [vrshlq_m_n_s, vrshlq_m_n_u])
> -;;
> -(define_insn "mve_vrshlq_m_n_<supf><mode>"
> -  [
> -   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
> -	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
> -		       (match_operand:SI 2 "s_register_operand" "r")
> -		       (match_operand:<MVE_VPRED> 3
> "vpr_register_operand" "Up")]
> -	 VRSHLQ_M_N))
> -  ]
> -  "TARGET_HAVE_MVE"
> -  "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %2"
> -  [(set_attr "type" "mve_move")
> -   (set_attr "length""8")])
> -
>  ;;
>  ;; [vshlq_m_r_u, vshlq_m_r_s])
>  ;;
> --
> 2.34.1
diff mbox series

Patch

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 593be83e0be..e7622fe752a 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -435,6 +435,16 @@  (define_int_iterator MVE_INT_N_BINARY_LOGIC   [
 		     VORRQ_N_S VORRQ_N_U
 		     ])
 
+(define_int_iterator MVE_RSHIFT_M_N   [
+		     VQRSHLQ_M_N_S VQRSHLQ_M_N_U
+		     VRSHLQ_M_N_S VRSHLQ_M_N_U
+		     ])
+
+(define_int_iterator MVE_RSHIFT_N   [
+		     VQRSHLQ_N_S VQRSHLQ_N_U
+		     VRSHLQ_N_S VRSHLQ_N_U
+		     ])
+
 (define_int_iterator MVE_FP_M_BINARY   [
 		     VADDQ_M_F
 		     VMULQ_M_F
@@ -526,7 +536,9 @@  (define_int_attr mve_insn [
 		 (VQRDMULHQ_M_S "vqrdmulh")
 		 (VQRDMULHQ_N_S "vqrdmulh")
 		 (VQRDMULHQ_S "vqrdmulh")
+		 (VQRSHLQ_M_N_S "vqrshl") (VQRSHLQ_M_N_U "vqrshl")
 		 (VQRSHLQ_M_S "vqrshl") (VQRSHLQ_M_U "vqrshl")
+		 (VQRSHLQ_N_S "vqrshl") (VQRSHLQ_N_U "vqrshl")
 		 (VQRSHLQ_S "vqrshl") (VQRSHLQ_U "vqrshl")
 		 (VQSHLQ_M_S "vqshl") (VQSHLQ_M_U "vqshl")
 		 (VQSHLQ_S "vqshl") (VQSHLQ_U "vqshl")
@@ -538,7 +550,9 @@  (define_int_attr mve_insn [
 		 (VRHADDQ_S "vrhadd") (VRHADDQ_U "vrhadd")
 		 (VRMULHQ_M_S "vrmulh") (VRMULHQ_M_U "vrmulh")
 		 (VRMULHQ_S "vrmulh") (VRMULHQ_U "vrmulh")
+		 (VRSHLQ_M_N_S "vrshl") (VRSHLQ_M_N_U "vrshl")
 		 (VRSHLQ_M_S "vrshl") (VRSHLQ_M_U "vrshl")
+		 (VRSHLQ_N_S "vrshl") (VRSHLQ_N_U "vrshl")
 		 (VRSHLQ_S "vrshl") (VRSHLQ_U "vrshl")
 		 (VSHLQ_M_S "vshl") (VSHLQ_M_U "vshl")
 		 (VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub") (VSUBQ_M_N_F "vsub")
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 6b88fdb8a7a..0d3343b6e29 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1373,17 +1373,18 @@  (define_expand "mve_vorrq_u<mode>"
 )
 
 ;;
-;; [vqrshlq_n_s, vqrshlq_n_u])
+;; [vqrshlq_n_s, vqrshlq_n_u]
+;; [vrshlq_n_u, vrshlq_n_s]
 ;;
-(define_insn "mve_vqrshlq_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
 	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
 		       (match_operand:SI 2 "s_register_operand" "r")]
-	 VQRSHLQ_N))
+	 MVE_RSHIFT_N))
   ]
   "TARGET_HAVE_MVE"
-  "vqrshl.<supf>%#<V_sz_elem>\t%q0, %2"
+  "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -1432,21 +1433,6 @@  (define_insn "mve_vqshluq_n_s<mode>"
   [(set_attr "type" "mve_move")
 ])
 
-;;
-;; [vrshlq_n_u, vrshlq_n_s])
-;;
-(define_insn "mve_vrshlq_n_<supf><mode>"
-  [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
-		       (match_operand:SI 2 "s_register_operand" "r")]
-	 VRSHLQ_N))
-  ]
-  "TARGET_HAVE_MVE"
-  "vrshl.<supf>%#<V_sz_elem>\t%q0, %2"
-  [(set_attr "type" "mve_move")
-])
-
 ;;
 ;; [vrshrq_n_s, vrshrq_n_u])
 ;;
@@ -3098,18 +3084,19 @@  (define_insn "mve_vqrdmlsdhxq_s<mode>"
 ])
 
 ;;
-;; [vqrshlq_m_n_s, vqrshlq_m_n_u])
+;; [vqrshlq_m_n_s, vqrshlq_m_n_u]
+;; [vrshlq_m_n_s, vrshlq_m_n_u]
 ;;
-(define_insn "mve_vqrshlq_m_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
 	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
 		       (match_operand:SI 2 "s_register_operand" "r")
 		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VQRSHLQ_M_N))
+	 MVE_RSHIFT_M_N))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vqrshlt.<supf>%#<V_sz_elem>	%q0, %2"
+  "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -3145,22 +3132,6 @@  (define_insn "mve_vrev64q_m_<supf><mode>"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
-;;
-;; [vrshlq_m_n_s, vrshlq_m_n_u])
-;;
-(define_insn "mve_vrshlq_m_n_<supf><mode>"
-  [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
-		       (match_operand:SI 2 "s_register_operand" "r")
-		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VRSHLQ_M_N))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vrshlt.<supf>%#<V_sz_elem>\t%q0, %2"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
 ;;
 ;; [vshlq_m_r_u, vshlq_m_r_s])
 ;;