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Fri, 5 May 2023 08:39:54 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX02.Emea.Arm.com (10.251.26.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 5 May 2023 08:39:53 +0000 Received: from e129018.arm.com (10.57.22.112) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Fri, 5 May 2023 08:39:53 +0000 To: , , , CC: Christophe Lyon Subject: [PATCH 19/23] arm: [MVE intrinsics] factorize vqrshrunb vqrshrunt vqshrunb vqshrunt Date: Fri, 5 May 2023 10:39:26 +0200 Message-ID: <20230505083930.101210-19-christophe.lyon@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505083930.101210-1-christophe.lyon@arm.com> References: <20230505083930.101210-1-christophe.lyon@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT020:EE_|DB9PR08MB9731:EE_|DBAEUR03FT052:EE_|AM9PR08MB6115:EE_ X-MS-Office365-Filtering-Correlation-Id: f3194ddc-24a3-4518-5147-08db4d445509 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT052.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB6115 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Christophe Lyon via Gcc-patches From: Christophe Lyon Reply-To: Christophe Lyon Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1765043457598974975?= X-GMAIL-MSGID: =?utf-8?q?1765043457598974975?= Factorize vqrshrunb, vqrshrunt, vqshrunb, vqshrunt so that they use existing patterns. 2022-09-08 Christophe Lyon gcc/ * config/arm/iterators.md (MVE_SHRN_N): Add VQRSHRUNBQ, VQRSHRUNTQ, VQSHRUNBQ, VQSHRUNTQ. (MVE_SHRN_M_N): Likewise. (mve_insn): Add vqrshrunb, vqrshrunt, vqshrunb, vqshrunt. (isu): Add VQRSHRUNBQ, VQRSHRUNTQ, VQSHRUNBQ, VQSHRUNTQ. (supf): Likewise. * config/arm/mve.md (mve_vqrshrunbq_n_s): Remove. (mve_vqrshruntq_n_s): Remove. (mve_vqshrunbq_n_s): Remove. (mve_vqshruntq_n_s): Remove. (mve_vqrshrunbq_m_n_s): Remove. (mve_vqrshruntq_m_n_s): Remove. (mve_vqshrunbq_m_n_s): Remove. (mve_vqshruntq_m_n_s): Remove. --- gcc/config/arm/iterators.md | 32 +++++++++ gcc/config/arm/mve.md | 140 +++--------------------------------- 2 files changed, 40 insertions(+), 132 deletions(-) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index d64c924a513..583206dac9e 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -471,8 +471,12 @@ (define_int_iterator MVE_RSHIFT_N [ (define_int_iterator MVE_SHRN_N [ VQRSHRNBQ_N_S VQRSHRNBQ_N_U VQRSHRNTQ_N_S VQRSHRNTQ_N_U + VQRSHRUNBQ_N_S + VQRSHRUNTQ_N_S VQSHRNBQ_N_S VQSHRNBQ_N_U VQSHRNTQ_N_S VQSHRNTQ_N_U + VQSHRUNBQ_N_S + VQSHRUNTQ_N_S VRSHRNBQ_N_S VRSHRNBQ_N_U VRSHRNTQ_N_S VRSHRNTQ_N_U VSHRNBQ_N_S VSHRNBQ_N_U @@ -482,8 +486,12 @@ (define_int_iterator MVE_SHRN_N [ (define_int_iterator MVE_SHRN_M_N [ VQRSHRNBQ_M_N_S VQRSHRNBQ_M_N_U VQRSHRNTQ_M_N_S VQRSHRNTQ_M_N_U + VQRSHRUNBQ_M_N_S + VQRSHRUNTQ_M_N_S VQSHRNBQ_M_N_S VQSHRNBQ_M_N_U VQSHRNTQ_M_N_S VQSHRNTQ_M_N_U + VQSHRUNBQ_M_N_S + VQSHRUNTQ_M_N_S VRSHRNBQ_M_N_S VRSHRNBQ_M_N_U VRSHRNTQ_M_N_S VRSHRNTQ_M_N_U VSHRNBQ_M_N_S VSHRNBQ_M_N_U @@ -594,6 +602,10 @@ (define_int_attr mve_insn [ (VQRSHRNBQ_N_S "vqrshrnb") (VQRSHRNBQ_N_U "vqrshrnb") (VQRSHRNTQ_M_N_S "vqrshrnt") (VQRSHRNTQ_M_N_U "vqrshrnt") (VQRSHRNTQ_N_S "vqrshrnt") (VQRSHRNTQ_N_U "vqrshrnt") + (VQRSHRUNBQ_M_N_S "vqrshrunb") + (VQRSHRUNBQ_N_S "vqrshrunb") + (VQRSHRUNTQ_M_N_S "vqrshrunt") + (VQRSHRUNTQ_N_S "vqrshrunt") (VQSHLQ_M_N_S "vqshl") (VQSHLQ_M_N_U "vqshl") (VQSHLQ_M_R_S "vqshl") (VQSHLQ_M_R_U "vqshl") (VQSHLQ_M_S "vqshl") (VQSHLQ_M_U "vqshl") @@ -604,6 +616,10 @@ (define_int_attr mve_insn [ (VQSHRNBQ_N_S "vqshrnb") (VQSHRNBQ_N_U "vqshrnb") (VQSHRNTQ_M_N_S "vqshrnt") (VQSHRNTQ_M_N_U "vqshrnt") (VQSHRNTQ_N_S "vqshrnt") (VQSHRNTQ_N_U "vqshrnt") + (VQSHRUNBQ_M_N_S "vqshrunb") + (VQSHRUNBQ_N_S "vqshrunb") + (VQSHRUNTQ_M_N_S "vqshrunt") + (VQSHRUNTQ_N_S "vqshrunt") (VQSUBQ_M_N_S "vqsub") (VQSUBQ_M_N_U "vqsub") (VQSUBQ_M_S "vqsub") (VQSUBQ_M_U "vqsub") (VQSUBQ_N_S "vqsub") (VQSUBQ_N_U "vqsub") @@ -640,10 +656,18 @@ (define_int_attr isu [ (VQRSHRNBQ_N_S "s") (VQRSHRNBQ_N_U "u") (VQRSHRNTQ_M_N_S "s") (VQRSHRNTQ_M_N_U "u") (VQRSHRNTQ_N_S "s") (VQRSHRNTQ_N_U "u") + (VQRSHRUNBQ_M_N_S "s") + (VQRSHRUNBQ_N_S "s") + (VQRSHRUNTQ_M_N_S "s") + (VQRSHRUNTQ_N_S "s") (VQSHRNBQ_M_N_S "s") (VQSHRNBQ_M_N_U "u") (VQSHRNBQ_N_S "s") (VQSHRNBQ_N_U "u") (VQSHRNTQ_M_N_S "s") (VQSHRNTQ_M_N_U "u") (VQSHRNTQ_N_S "s") (VQSHRNTQ_N_U "u") + (VQSHRUNBQ_M_N_S "s") + (VQSHRUNBQ_N_S "s") + (VQSHRUNTQ_M_N_S "s") + (VQSHRUNTQ_N_S "s") (VRSHRNBQ_M_N_S "i") (VRSHRNBQ_M_N_U "i") (VRSHRNBQ_N_S "i") (VRSHRNBQ_N_U "i") (VRSHRNTQ_M_N_S "i") (VRSHRNTQ_M_N_U "i") @@ -1816,6 +1840,14 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s") (VQRDMULHQ_M_N_S "s") (VQDMULHQ_S "s") (VQRDMULHQ_S "s") + (VQRSHRUNBQ_M_N_S "s") + (VQRSHRUNBQ_N_S "s") + (VQRSHRUNTQ_M_N_S "s") + (VQRSHRUNTQ_N_S "s") + (VQSHRUNBQ_M_N_S "s") + (VQSHRUNBQ_N_S "s") + (VQSHRUNTQ_M_N_S "s") + (VQSHRUNTQ_N_S "s") ]) ;; Both kinds of return insn. diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index d64a075c7bb..20ce7ecb3d6 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -2166,8 +2166,12 @@ (define_insn "mve_vcvtq_m_to_f_" ;; ;; [vqrshrnbq_n_u, vqrshrnbq_n_s] ;; [vqrshrntq_n_u, vqrshrntq_n_s] +;; [vqrshrunbq_n_s] +;; [vqrshruntq_n_s] ;; [vqshrnbq_n_u, vqshrnbq_n_s] ;; [vqshrntq_n_u, vqshrntq_n_s] +;; [vqshrunbq_n_s] +;; [vqshruntq_n_s] ;; [vrshrnbq_n_s, vrshrnbq_n_u] ;; [vrshrntq_n_u, vrshrntq_n_s] ;; [vshrnbq_n_u, vshrnbq_n_s] @@ -2186,22 +2190,6 @@ (define_insn "@mve_q_n_" [(set_attr "type" "mve_move") ]) -;; -;; [vqrshrunbq_n_s]) -;; -(define_insn "mve_vqrshrunbq_n_s" - [ - (set (match_operand: 0 "s_register_operand" "=w") - (unspec: [(match_operand: 1 "s_register_operand" "0") - (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "" "")] - VQRSHRUNBQ_N_S)) - ] - "TARGET_HAVE_MVE" - "vqrshrunb.s%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") -]) - ;; ;; [vrmlaldavhaq_s vrmlaldavhaq_u]) ;; @@ -4002,54 +3990,6 @@ (define_insn "mve_vqmovuntq_m_s" [(set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vqrshruntq_n_s]) -;; -(define_insn "mve_vqrshruntq_n_s" - [ - (set (match_operand: 0 "s_register_operand" "=w") - (unspec: [(match_operand: 1 "s_register_operand" "0") - (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "" "")] - VQRSHRUNTQ_N_S)) - ] - "TARGET_HAVE_MVE" - "vqrshrunt.s%# %q0, %q2, %3" - [(set_attr "type" "mve_move") -]) - -;; -;; [vqshrunbq_n_s]) -;; -(define_insn "mve_vqshrunbq_n_s" - [ - (set (match_operand: 0 "s_register_operand" "=w") - (unspec: [(match_operand: 1 "s_register_operand" "0") - (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "" "")] - VQSHRUNBQ_N_S)) - ] - "TARGET_HAVE_MVE" - "vqshrunb.s%# %q0, %q2, %3" - [(set_attr "type" "mve_move") -]) - -;; -;; [vqshruntq_n_s]) -;; -(define_insn "mve_vqshruntq_n_s" - [ - (set (match_operand: 0 "s_register_operand" "=w") - (unspec: [(match_operand: 1 "s_register_operand" "0") - (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "" "")] - VQSHRUNTQ_N_S)) - ] - "TARGET_HAVE_MVE" - "vqshrunt.s%# %q0, %q2, %3" - [(set_attr "type" "mve_move") -]) - ;; ;; [vrev32q_m_f]) ;; @@ -4892,8 +4832,12 @@ (define_insn "mve_vmlaldavaxq_p_" ;; ;; [vqrshrnbq_m_n_u, vqrshrnbq_m_n_s] ;; [vqrshrntq_m_n_s, vqrshrntq_m_n_u] +;; [vqrshrunbq_m_n_s] +;; [vqrshruntq_m_n_s] ;; [vqshrnbq_m_n_u, vqshrnbq_m_n_s] ;; [vqshrntq_m_n_s, vqshrntq_m_n_u] +;; [vqshrunbq_m_n_s] +;; [vqshruntq_m_n_s] ;; [vrshrnbq_m_n_u, vrshrnbq_m_n_s] ;; [vrshrntq_m_n_u, vrshrntq_m_n_s] ;; [vshrnbq_m_n_s, vshrnbq_m_n_u] @@ -5100,74 +5044,6 @@ (define_insn "mve_vqdmulltq_m_s" [(set_attr "type" "mve_move") (set_attr "length""8")]) -;; -;; [vqrshrunbq_m_n_s]) -;; -(define_insn "mve_vqrshrunbq_m_n_s" - [ - (set (match_operand: 0 "s_register_operand" "=w") - (unspec: [(match_operand: 1 "s_register_operand" "0") - (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "" "") - (match_operand: 4 "vpr_register_operand" "Up")] - VQRSHRUNBQ_M_N_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vqrshrunbt.s%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vqrshruntq_m_n_s]) -;; -(define_insn "mve_vqrshruntq_m_n_s" - [ - (set (match_operand: 0 "s_register_operand" "=w") - (unspec: [(match_operand: 1 "s_register_operand" "0") - (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "" "") - (match_operand: 4 "vpr_register_operand" "Up")] - VQRSHRUNTQ_M_N_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vqrshruntt.s%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vqshrunbq_m_n_s]) -;; -(define_insn "mve_vqshrunbq_m_n_s" - [ - (set (match_operand: 0 "s_register_operand" "=w") - (unspec: [(match_operand: 1 "s_register_operand" "0") - (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "" "") - (match_operand: 4 "vpr_register_operand" "Up")] - VQSHRUNBQ_M_N_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vqshrunbt.s%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - -;; -;; [vqshruntq_m_n_s]) -;; -(define_insn "mve_vqshruntq_m_n_s" - [ - (set (match_operand: 0 "s_register_operand" "=w") - (unspec: [(match_operand: 1 "s_register_operand" "0") - (match_operand:MVE_5 2 "s_register_operand" "w") - (match_operand:SI 3 "" "") - (match_operand: 4 "vpr_register_operand" "Up")] - VQSHRUNTQ_M_N_S)) - ] - "TARGET_HAVE_MVE" - "vpst\;vqshruntt.s%#\t%q0, %q2, %3" - [(set_attr "type" "mve_move") - (set_attr "length""8")]) - ;; ;; [vrmlaldavhaq_p_u]) ;;