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[8.43.85.97]) by mx.google.com with ESMTPS id tk25-20020a170907c29900b00965b6e73deasi50156ejc.119.2023.05.03.22.57.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 May 2023 22:57:38 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=LUdbGQ4J; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F21313857341 for ; Thu, 4 May 2023 05:57:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F21313857341 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683179857; bh=YkYX50xxyK3pEyL2XYtf/M4hNqNyMpyB9byMyi6U5HM=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=LUdbGQ4JeadYwI4v9Mv3VueI2vbwgoo2fMNk9Ve5+zWO/m1IfGmYNYHPbWes5Mk9L 6EKsk7TMf4zrAWMOGMKlibSOx6mxjikvfb+HPmSp8IgxNRucQp0kCCThKpwFibxxyE unwz13ccxslKobXbTqBAIqKVWtoVlBxPM5oQAp44= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id 333083858D28; Thu, 4 May 2023 05:56:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 333083858D28 X-IronPort-AV: E=McAfee;i="6600,9927,10699"; a="414307162" X-IronPort-AV: E=Sophos;i="5.99,249,1677571200"; d="scan'208";a="414307162" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2023 22:56:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10699"; a="696885630" X-IronPort-AV: E=Sophos;i="5.99,249,1677571200"; d="scan'208";a="696885630" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga002.jf.intel.com with ESMTP; 03 May 2023 22:56:47 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 98F711005174; Thu, 4 May 2023 13:56:46 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, linkw@gcc.gnu.org, dje.gcc@gmail.com Subject: [PATCH] [powerpc] Add a peephole2 to eliminate redundant move from VSX_REGS to GENERAL_REGS when it's from memory. Date: Thu, 4 May 2023 13:54:46 +0800 Message-Id: <20230504055446.1675940-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.39.1.388.g2fc9e9ca3c MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764942002965596497?= X-GMAIL-MSGID: =?utf-8?q?1764942002965596497?= r14-172-g0368d169492017 use NO_REGS instead of GENERAL_REGS in memory cost calculation when preferred register class is unkown. + /* Costs for NO_REGS are used in cost calculation on the + 1st pass when the preferred register classes are not + known yet. In this case we take the best scenario. */ It regressed gcc.target/powerpc/dform-3.c which has inline asm explicitly put a vector mode into a general register, then create an extra move. RA doesn't allocate GENERAL_REGS for it because the backend pattern explicitly disparage the alternative (, r), (??r, Y) which moves from GENERAL_REGS/MEM to GENERAL_REGS. (define_insn "vsx_mov_64bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, r, we, ?wQ, ?&r, ??r, ??Y, , wa, v, wa, wa, ?wa, v, , wZ, v") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, we, r, r, wQ, Y, r, r, wE, jwM, eQ, eP, ?jwM, W, , v, wZ"))] "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (mode) && (register_operand (operands[0], mode) || register_operand (operands[1], mode))" { return rs6000_output_move_128bit (operands); } Normally the extra move can be eliminated by pass_reload when src and dest has same reg_class, but for that case, src and dest have different reg_classes. The patch adds a peephole2 to eliminate the extra move. Bootstrapped and regtested on powerpc64le-linux-gnu. Ok for trunk? gcc/ChangeLog: PR target/109610 * config/rs6000/vsx.md (define_peephole2): New peephole2 to catch memory loads to VSX_REGS and then moves to GENERAL_REGS. --- gcc/config/rs6000/vsx.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 7d845df5c2d..a0808ccff9a 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1075,6 +1075,16 @@ (define_peephole2 && peep2_reg_dead_p (2, operands[0])" [(set (match_dup 2) (match_dup 1))]) +;; Peephole to catch memory loads to VSX_REG and then moves to GENERAL_REGS. +(define_peephole2 + [(set (match_operand:VSX_M 0 "vsx_register_operand") + (match_operand:VSX_M 1 "memory_operand")) + (set (match_operand:VSX_M 2 "int_reg_operand") + (match_dup 0))] + "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (mode) + && peep2_reg_dead_p (2, operands[0])" + [(set (match_dup 2) (match_dup 1))]) + ;; Peephole to catch memory to memory transfers for TImode if TImode landed in ;; VSX registers on a little endian system. The vector types and IEEE 128-bit ;; floating point are handled by the more generic swap elimination pass.