From patchwork Thu May 4 03:25:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 89902 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp26830vqo; Wed, 3 May 2023 20:28:24 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6CjCTRalDYMw1JFnNc5OYXhI2RHpTWE4QnoIi8atG0Rm6H+PXgKqXGKFxbpYQDnkKoMC0m X-Received: by 2002:a17:907:5cb:b0:947:55ad:dd00 with SMTP id wg11-20020a17090705cb00b0094755addd00mr4642153ejb.26.1683170904575; Wed, 03 May 2023 20:28:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683170904; cv=none; d=google.com; s=arc-20160816; b=vc4x3co5w04FKnQ57iv4+cjvmLZiqnWa2cUCDsR5YC82dxZIYYljwxE1zDBO4/Lxm1 Rz/Pk6bpXt/TDcZXfHWCKUDzDZTgE+nLlJJjCKlgjt6E+/U87LN3CP+qDLgRFOVU9HvY +/G88dc9+0mpG/YIVLwGACvecpKWCdPnhsQGDCe5ITo/ToRhgfCkBxCPZpisV0t7fxYF 3djrV+gq93E/QFS9Oz7OJubjhKUDjIlQCbEMVKyWE1S/ik9YvuGLEaEN4QyEJGVnpO/9 HaELkd6RnxYFmyKRPnTC1h5Uf+QEe53LLTf0ATUsYqgp1GL8MLeuacIkG87mgHxunzRg nZpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=5FC43a72XZfj+jFjfcmkP6pJX8TN8ml/u0nMRrCnTqQ=; b=YIbYzDZh6rJmk0op/C2T6AvWKbFNUh7/IcbzNcGrl/OV7SuiI5frNifp79NnhGbj96 Heqvh7/kKiqWJ0tMD85TcgR/pyS1z0fieWzw3s6w+exLNsGHvWfhFzTXjRjGjyXT4/fJ 2Ek4OdiBjvv5f+4SSSm9nRFknjMd4JMTYyJ/Nk1M3VBXdiWDtqV65RZNwXWCcW2Qz6PV uPz7RTeTGxxG4kz3ERKPgx/m3YhZEByzg9V7njGLDjtfWz3oQ9srk7CplOoyx6bDh1JO 2l3LZ+tPbN/MoWih1A1T/3Ed2xRHWSWuHax0dK+ggeKOKbiov9zg4vJFcVQkHSTY67ij IPvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=yENsOh6y; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id e22-20020a50ec96000000b0050bc4d789a3si2212942edr.118.2023.05.03.20.28.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 May 2023 20:28:24 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=yENsOh6y; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3BD483857735 for ; Thu, 4 May 2023 03:28:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3BD483857735 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1683170903; bh=5FC43a72XZfj+jFjfcmkP6pJX8TN8ml/u0nMRrCnTqQ=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=yENsOh6yJEpI7K5FbcuzV7cw4hmuQ9/gqSWAJZ3E13NTq1D+P9w/LSfBB2xKuLpNC YVN+DQHwg6Nrkfl5HANocbV+rbcupRWODm5Zzm2AJMq13yMqOplyX0z2kyGVDkxpCD lmjXVQk41kdNhHvOb8a+4/qxj+zUgdeKZDTyq+lo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by sourceware.org (Postfix) with ESMTPS id 951DA3858D28 for ; Thu, 4 May 2023 03:27:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 951DA3858D28 X-IronPort-AV: E=McAfee;i="6600,9927,10699"; a="348867979" X-IronPort-AV: E=Sophos;i="5.99,249,1677571200"; d="scan'208";a="348867979" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2023 20:27:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10699"; a="1026768683" X-IronPort-AV: E=Sophos;i="5.99,249,1677571200"; d="scan'208";a="1026768683" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga005.fm.intel.com with ESMTP; 03 May 2023 20:27:35 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 3FB7410056FA; Thu, 4 May 2023 11:27:35 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com Subject: [PATCH v2] Canonicalize vec_merge when mask is constant. Date: Thu, 4 May 2023 11:25:35 +0800 Message-Id: <20230504032535.1368877-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.39.1.388.g2fc9e9ca3c In-Reply-To: <1995c643-47bb-6376-ce72-d5440e59196b@gmail.com> References: <1995c643-47bb-6376-ce72-d5440e59196b@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763666192588852442?= X-GMAIL-MSGID: =?utf-8?q?1764932614347048287?= Here's update patch with documents in md.texi. Ok for trunk? -------------- Use swap_communattive_operands_p for canonicalization. When both value has same operand precedence value, then first bit in the mask should select first operand. The canonicalization should help backends for pattern match. .i.e. x86 backend has lots of vec_merge patterns, combine will create any form of vec_merge(mask, or inverted mask), then backend need to add 2 patterns to match exact 1 instruction. The canonicalization can simplify 2 patterns to 1. gcc/ChangeLog: * combine.cc (maybe_swap_commutative_operands): Canonicalize vec_merge when mask is constant. * doc/md.texi: Document vec_merge canonicalization. --- gcc/combine.cc | 22 ++++++++++++++++++++++ gcc/doc/md.texi | 7 +++++++ 2 files changed, 29 insertions(+) diff --git a/gcc/combine.cc b/gcc/combine.cc index 0106092e456..5aa0ec5c45a 100644 --- a/gcc/combine.cc +++ b/gcc/combine.cc @@ -5631,6 +5631,28 @@ maybe_swap_commutative_operands (rtx x) SUBST (XEXP (x, 0), XEXP (x, 1)); SUBST (XEXP (x, 1), temp); } + + unsigned n_elts = 0; + if (GET_CODE (x) == VEC_MERGE + && CONST_INT_P (XEXP (x, 2)) + && GET_MODE_NUNITS (GET_MODE (x)).is_constant (&n_elts) + && (swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)) + /* Two operands have same precedence, then + first bit of mask select first operand. */ + || (!swap_commutative_operands_p (XEXP (x, 1), XEXP (x, 0)) + && !(UINTVAL (XEXP (x, 2)) & 1)))) + { + rtx temp = XEXP (x, 0); + unsigned HOST_WIDE_INT sel = UINTVAL (XEXP (x, 2)); + unsigned HOST_WIDE_INT mask = HOST_WIDE_INT_1U; + if (n_elts == HOST_BITS_PER_WIDE_INT) + mask = -1; + else + mask = (HOST_WIDE_INT_1U << n_elts) - 1; + SUBST (XEXP (x, 0), XEXP (x, 1)); + SUBST (XEXP (x, 1), temp); + SUBST (XEXP (x, 2), GEN_INT (~sel & mask)); + } } /* Simplify X, a piece of RTL. We just operate on the expression at the diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 07bf8bdebff..aff9b7348ce 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -8215,6 +8215,13 @@ second operand. If a machine only supports a constant as the second operand, only patterns that match a constant in the second operand need be supplied. +@cindex @code{vec_merge}, canonicalization of +@item +For the @code{vec_merge} with constant mask(the third operand), the first +and the second operand can be exchanged by inverting the mask. In such cases, +a constant is always made the second operand, otherwise the least significant +bit of the mask is always set(select the first operand first). + @item For associative operators, a sequence of operators will always chain to the left; for instance, only the left operand of an integer @code{plus}