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[8.43.85.97]) by mx.google.com with ESMTPS id m20-20020aa7d354000000b00504adca9a25si12842611edr.164.2023.04.28.08.21.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Apr 2023 08:21:54 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="Ge/WfPup"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 466983858C60 for ; Fri, 28 Apr 2023 15:21:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 466983858C60 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682695313; bh=czfqh79sOb2T4gYw1/9ExSdsjBolbHv0CShJIrx2qQ8=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=Ge/WfPupUnnjM1cLE3JDX09W9XExM7C7guQV4nvP1V84krJhWbEwOXYVS025aDsTk LeUCt660Y9IecaA3ZhLRX8Tar3MFoh//LFfDU1s0lPXC3Qc8C2obfBTzxxfwppXwCZ 80pt6NSJ8lSVa2OZrcVPrHZrNyVgycnBa8mxIU80= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by sourceware.org (Postfix) with ESMTPS id 93A213858422 for ; Fri, 28 Apr 2023 15:21:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 93A213858422 X-IronPort-AV: E=McAfee;i="6600,9927,10694"; a="347799356" X-IronPort-AV: E=Sophos;i="5.99,234,1677571200"; d="scan'208";a="347799356" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Apr 2023 08:21:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10694"; a="727577228" X-IronPort-AV: E=Sophos;i="5.99,234,1677571200"; d="scan'208";a="727577228" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga001.jf.intel.com with ESMTP; 28 Apr 2023 08:21:04 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id F3A8B10083A5; Fri, 28 Apr 2023 23:21:03 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMSET Date: Fri, 28 Apr 2023 23:21:02 +0800 Message-Id: <20230428152102.1653600-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764433921514966915?= X-GMAIL-MSGID: =?utf-8?q?1764433921514966915?= From: Pan Li When some RVV integer compare operators act on the same vector registers without mask. They can be simplified to VMSET. This PATCH allows the eq, le, leu, ge, geu to perform such kind of the simplification by adding one macro in riscv for simplify rtx. Given we have: vbool1_t test_shortcut_for_riscv_vmseq_case_0(vint8m8_t v1, size_t vl) { return __riscv_vmseq_vv_i8m8_b1(v1, v1, vl); } Before this patch: vsetvli zero,a2,e8,m8,ta,ma vl8re8.v v8,0(a1) vmseq.vv v8,v8,v8 vsetvli a5,zero,e8,m8,ta,ma vsm.v v8,0(a0) ret After this patch: vsetvli zero,a2,e8,m8,ta,ma vmset.m v1 <- optimized to vmset.m vsetvli a5,zero,e8,m8,ta,ma vsm.v v1,0(a0) ret As above, we may have one instruction eliminated and require less vector registers. Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv.h (VECTOR_STORE_FLAG_VALUE): Add new macro consumed by simplify_rtx. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: Adjust test check condition. --- gcc/config/riscv/riscv.h | 5 +++++ .../riscv/rvv/base/integer_compare_insn_shortcut.c | 6 +----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 13038a39e5c..4473115d3a9 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -1096,4 +1096,9 @@ extern void riscv_remove_unneeded_save_restore_calls (void); #define DWARF_REG_TO_UNWIND_COLUMN(REGNO) \ ((REGNO == RISCV_DWARF_VLENB) ? (FIRST_PSEUDO_REGISTER + 1) : REGNO) +/* Like s390, riscv also defined this macro for the vector comparision. Then + the simplify-rtx relational_result will canonicalize the result to the + CONST1_RTX for the simplification. */ +#define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE)) + #endif /* ! GCC_RISCV_H */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c index 8954adad09d..1bca8467a16 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c @@ -283,9 +283,5 @@ vbool64_t test_shortcut_for_riscv_vmsgeu_case_6(vuint8mf8_t v1, size_t vl) { return __riscv_vmsgeu_vv_u8mf8_b64(v1, v1, vl); } -/* { dg-final { scan-assembler-times {vmseq\.vv\sv[0-9],\s*v[0-9],\s*v[0-9]} 7 } } */ -/* { dg-final { scan-assembler-times {vmsle\.vv\sv[0-9],\s*v[0-9],\s*v[0-9]} 7 } } */ -/* { dg-final { scan-assembler-times {vmsleu\.vv\sv[0-9],\s*v[0-9],\s*v[0-9]} 7 } } */ -/* { dg-final { scan-assembler-times {vmsge\.vv\sv[0-9],\s*v[0-9],\s*v[0-9]} 7 } } */ -/* { dg-final { scan-assembler-times {vmsgeu\.vv\sv[0-9],\s*v[0-9],\s*v[0-9]} 7 } } */ /* { dg-final { scan-assembler-times {vmclr\.m\sv[0-9]} 35 } } */ +/* { dg-final { scan-assembler-times {vmset\.m\sv[0-9]} 35 } } */