From patchwork Fri Apr 28 11:29:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 88609 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp863064vqo; Fri, 28 Apr 2023 04:36:37 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5kTSZd9oHFRMu2fNpa6xgJkbYIcXfSQ6di6vURBEbYtF23Ae9JgvYTk2LuDU6vuhvk3lhD X-Received: by 2002:a17:907:7254:b0:94e:c40b:71e3 with SMTP id ds20-20020a170907725400b0094ec40b71e3mr10536428ejc.5.1682681796783; Fri, 28 Apr 2023 04:36:36 -0700 (PDT) Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id h26-20020a1709063c1a00b0094f050da728si14844157ejg.581.2023.04.28.04.36.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Apr 2023 04:36:36 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=bO24kCOC; arc=fail (signature failed); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F0CC53850841 for ; Fri, 28 Apr 2023 11:34:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F0CC53850841 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1682681680; bh=MNJGwHDORg80CXuC/Jnb+Nx34q5uGHZkppAMAwzYHBM=; h=To:CC:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=bO24kCOCAobr7JnbVMhpGu3SGXArSuDge5lBuYAV1B4Uqvlsiz/Q853lKDXEnG6mB wQH/aX8baG+BlC3vyt6z+L3iZITy6Y3q/mrrjpePOrCdZCOkovphxV+mltPBz1PxmM 2Tssklf2juFogZ57HEcsR8bNu/TWb7PphPk5nfwQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2047.outbound.protection.outlook.com [40.107.105.47]) by sourceware.org (Postfix) with ESMTPS id A1F3B3857012 for ; Fri, 28 Apr 2023 11:32:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A1F3B3857012 Received: from AS9PR06CA0584.eurprd06.prod.outlook.com (2603:10a6:20b:486::9) by AS8PR08MB10313.eurprd08.prod.outlook.com (2603:10a6:20b:5c1::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6340.22; Fri, 28 Apr 2023 11:32:35 +0000 Received: from AM7EUR03FT043.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:486:cafe::10) by AS9PR06CA0584.outlook.office365.com (2603:10a6:20b:486::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6340.23 via Frontend Transport; Fri, 28 Apr 2023 11:32:35 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM7EUR03FT043.mail.protection.outlook.com (100.127.140.160) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6340.23 via Frontend Transport; Fri, 28 Apr 2023 11:32:35 +0000 Received: ("Tessian outbound e13c2446394c:v136"); Fri, 28 Apr 2023 11:32:35 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: c416b64ec8bc47f4 X-CR-MTA-TID: 64aa7808 Received: from d232d3e9f117.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 9DAEA7C8-78CB-4088-A9C3-EA2CD8A7CD16.1; Fri, 28 Apr 2023 11:30:42 +0000 Received: from EUR03-AM7-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id d232d3e9f117.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 28 Apr 2023 11:30:42 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=FkJNuD0lLTZVRL/mPTlHSutjfpQGJ6/QzMKLw/lvzGZviolucHSFUyk55flABeHlnQJC1PPElnY5micAXH0wBwpdGn4uzWOhl7a1km8x5gBEIxpBloIGS+X8yXk2dYcfkqsNCOkYeG+h/BZeJnnOw/FEdxp+8mOnT3XqPfbbsxfpUbAh9Sx/CGA9XCpy/Hw4scOyeq8mE8iZ8SViIuY3ItiXdWqmm9EkhZ1F4KLe4GFG9HcPRde1RAvs3Z0HUdDHB7ZqxE/gInm35/l/dmy0LnYI0/m65UrL7Qt1H7ef7GQsvuCVXL6UdEKBh78lnzlj1t7oaig0P9Abiax84qh7aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MNJGwHDORg80CXuC/Jnb+Nx34q5uGHZkppAMAwzYHBM=; b=bxN7BRvTQTEMckHjzjPqBd25PfD0A6iBy92+Zx0VU2vtRDuZCgNdFkVBBCyANozNZiLfqUpz/luNCykyDyFed8HDxyn0RIJm2/jhWOAixfemkXtkmHhxe4fk65YdISlW/f7v+d0H3wc8FW94um3w4AYAAmh9wz4vb/aHtEs8yxBWGCVqR2KDJrYWtYA/eohmj5Kw66drQsaGRj25N+OHYrBuMfpGNgP+xwWVmpkrpqwFxjAZBZRD4TaDjUwue26Yw5d2vdGO5DU+f7kRt/cy6pFPvaaOxES/6wXd/nWtwCGXCC6TgZ2gFfHA/z4rDHJV6JkIdlqkqL7Z/WKQGFfIZg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none Received: from AM5PR04CA0001.eurprd04.prod.outlook.com (2603:10a6:206:1::14) by DB9PR08MB10377.eurprd08.prod.outlook.com (2603:10a6:10:3db::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6340.24; Fri, 28 Apr 2023 11:30:36 +0000 Received: from AM7EUR03FT064.eop-EUR03.prod.protection.outlook.com (2603:10a6:206:1:cafe::1b) by AM5PR04CA0001.outlook.office365.com (2603:10a6:206:1::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6340.24 via Frontend Transport; Fri, 28 Apr 2023 11:30:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AM7EUR03FT064.mail.protection.outlook.com (100.127.140.127) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6340.24 via Frontend Transport; Fri, 28 Apr 2023 11:30:36 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Fri, 28 Apr 2023 11:30:31 +0000 Received: from e124257.nice.arm.com (10.34.101.64) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.23 via Frontend Transport; Fri, 28 Apr 2023 11:30:31 +0000 To: CC: , , Andrea Corallo Subject: [PATCH 02/10] arm: Fix vstrwq* backend + testsuite Date: Fri, 28 Apr 2023 13:29:54 +0200 Message-ID: <20230428113002.482343-2-andrea.corallo@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230428113002.482343-1-andrea.corallo@arm.com> References: <20230428113002.482343-1-andrea.corallo@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT064:EE_|DB9PR08MB10377:EE_|AM7EUR03FT043:EE_|AS8PR08MB10313:EE_ X-MS-Office365-Filtering-Correlation-Id: 228188b1-2b72-4dda-7e3b-08db47dc43c6 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: aowtbGLdkr12CIt+z8k7ATnDryQHXuATkXOOJTOTafHQp6ONz3ICGEiwUhJ1ZaLkSmtfKx6wVXvq8v6MtPfxkzb/0zFBMNWjc9kL8ab8UvvXTiqkeLgrkRy19zIPK+DKx4ZvHkWT11sOi8HMy5GD/LBDaWPhNnvrTDD37Oxl5jxs+/BEv1BHgBPmj4cDUmgSp3PSUa1SwaKj5vjGd+5QI7RKYA/rlz0HdtnWEhjY1xw4n5KeSjL7g492yWLCCHYefs80s8LqjUn6CqMpIFe5+c8uHGtEGgkktrBuD7JFvFdN40U0E3deA0mI9VEDeP7UG+ohxsSDCbj/+pZLw0149QtgT0u7DlfEbN6qeDi4KQQsVSsgctK2OQak3auuR0BGSK2pQS49XMjTe+4BFmmpddpCTYaeMQmU/zcHvN5DVYhc3a+r/P+KXFOYVv4ZbiYqbfGCW7mIw4iCLVUZxu3rLikux0dQqJsPjZlm5U0Teo2XOSsyaU0B1EswDYSrotDE/PqYSP8xL/5SbXTNu37LESPtmkaNHssZVCIaGBMIG1oyzl1n332lt3Xd6XT9tAUYb1FpSogUx4Qyg0ml+S/SP2s5YfnYMFqmU0WAx88LYdOtgLqw+I6oinbj9wVhL47DPY2xN6WXRAUuBMupEyFcwVHhCdE3GtkGD4dZgDuW+zezP5xEzD/XAj/Hd6rsm6UY2vuId9FhxR0ewvt9xfm0zTE54M3fUnGwVUsjM/wKk9ezPxjlsmQ9et7qyB0j0L2yfTd6pwj8SMmD63YqXl2exw== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(396003)(39860400002)(136003)(346002)(376002)(451199021)(36840700001)(46966006)(8676002)(8936002)(83380400001)(41300700001)(47076005)(1076003)(26005)(54906003)(336012)(30864003)(316002)(2906002)(426003)(5660300002)(44832011)(36860700001)(84970400001)(70206006)(70586007)(6916009)(4326008)(86362001)(2616005)(34020700004)(186003)(82310400005)(82740400003)(40480700001)(356005)(81166007)(478600001)(36756003)(6666004)(7696005)(36900700001)(579004)(559001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB10377 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM7EUR03FT043.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: fb80002d-9c31-490b-8a79-08db47dbfcbf X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yvrQyGPBswPOBBHvLkPWIbf+lCYpbv4+b9xhdfQ39cvV/njuFVrjneiPcJysEFxWtsgZevyjTAUHlHq+xaWyrVtZ365Xdu1VUm05HAgXw73CkpSriDm1ghGCcSiOC2hfgQa1iCbEh31V7f+E5r8nDz8D0tomSakkJaXYkAUEt+MNeXWKbPBueIbUMqAkvoNdQQ/ktuBtL8OMZ8gzUQfsIdbcNoeyTEx7g8XGDmeKqvSgbgVkYyNeBb7+OpWGd7ybnTGBeuBnVmq2jdOHaZI2Yr7F7nkmermA7CaHEhNtinjGomFEBaYRDQprWczN0Av2PQqWoiKLXXTZl5+mFwXoCf0oiJ9gR9CaYSBfmthhpWA/Sdv2QbE9Jlcmn5UMzdRW1BKJ8jUU49CUPcAxXZKHyLbUcLNakqmkS5eODxae2VWlUf37xXmzDCP3aXXJl3/lUlokTjd6bHHc8NeW1liM/g44sOVR0SXeynda13VrFMBCaE8ZO4gtuHImUrHBPzf6DYqNjbUytvceUNqu0LxOUEi19ZsTRvwEPIBA26K5CYvb88ZIQmQEK25CTggy34sUdF2z2nOhH9sTwmbrE6UONvdRMaoA1pCzOE85MSNfiXo2hYod5OflxP5Zclpmc+UvZOBWKO0yGL1bB5G/Q/bAKAqxvz5qPkeLURYRTijWVCW2gcj6Ig460UtTkzPvH8bjQt+0t481lStOaPJYg3/Tt7AMOMXSJuBZcwywjyA2JFjOjmsKu2snfs1OaQ+g0oliM/ikE9hAV8XVGZInDoFWvg== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230028)(4636009)(136003)(396003)(376002)(346002)(39860400002)(451199021)(36840700001)(46966006)(40470700004)(84970400001)(30864003)(2906002)(70586007)(70206006)(2616005)(86362001)(44832011)(336012)(5660300002)(8676002)(8936002)(478600001)(40460700003)(36756003)(6916009)(316002)(4326008)(41300700001)(7696005)(54906003)(6666004)(40480700001)(36860700001)(81166007)(186003)(83380400001)(82740400003)(426003)(26005)(1076003)(47076005)(82310400005)(34020700004)(579004)(559001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2023 11:32:35.7891 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 228188b1-2b72-4dda-7e3b-08db47dc43c6 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT043.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB10313 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764419747972445805?= X-GMAIL-MSGID: =?utf-8?q?1764419747972445805?= Hi all, this patch fixes the vstrwq* MVE instrinsics failing to emit the correct sequence of instruction due to a missing predicates. Also the immediate range is fixed to be multiples of 2 up between [-252, 252]. Best Regards Andrea gcc/ChangeLog: * config/arm/constraints.md (mve_vldrd_immediate): Move it to predicates.md. (Ri): Move constraint definition from predicates.md. (Rl): Define new constraint. * config/arm/mve.md (mve_vstrwq_scatter_base_wb_p_v4si): Add missing constraint. (mve_vstrwq_scatter_base_wb_p_fv4sf): Add missing Up constraint for op 1, use mve_vstrw_immediate predicate and Rl constraint for op 2. Fix asm output spacing. (mve_vstrdq_scatter_base_wb_p_v2di): Add missing constraint. * config/arm/predicates.md (Ri) Move constraint to constraints.md (mve_vldrd_immediate): Move it from constraints.md. (mve_vstrw_immediate): New predicate. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vstrwq_f32.c: Use check-function-bodies instead of scan-assembler checks. Use extern "C" for C++ testing. * gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vstrwq_u32.c: Likewise. --- gcc/config/arm/constraints.md | 20 ++++++++-- gcc/config/arm/mve.md | 10 ++--- gcc/config/arm/predicates.md | 14 +++---- .../arm/mve/intrinsics/vstrwq_f32.c | 32 ++++++++++++--- .../arm/mve/intrinsics/vstrwq_p_f32.c | 40 ++++++++++++++++--- .../arm/mve/intrinsics/vstrwq_p_s32.c | 40 ++++++++++++++++--- .../arm/mve/intrinsics/vstrwq_p_u32.c | 40 ++++++++++++++++--- .../arm/mve/intrinsics/vstrwq_s32.c | 32 ++++++++++++--- .../mve/intrinsics/vstrwq_scatter_base_f32.c | 28 +++++++++++-- .../intrinsics/vstrwq_scatter_base_p_f32.c | 36 +++++++++++++++-- .../intrinsics/vstrwq_scatter_base_p_s32.c | 36 +++++++++++++++-- .../intrinsics/vstrwq_scatter_base_p_u32.c | 36 +++++++++++++++-- .../mve/intrinsics/vstrwq_scatter_base_s32.c | 28 +++++++++++-- .../mve/intrinsics/vstrwq_scatter_base_u32.c | 28 +++++++++++-- .../intrinsics/vstrwq_scatter_base_wb_f32.c | 32 ++++++++++++--- .../intrinsics/vstrwq_scatter_base_wb_p_f32.c | 40 ++++++++++++++++--- .../intrinsics/vstrwq_scatter_base_wb_p_s32.c | 40 ++++++++++++++++--- .../intrinsics/vstrwq_scatter_base_wb_p_u32.c | 40 ++++++++++++++++--- .../intrinsics/vstrwq_scatter_base_wb_s32.c | 32 ++++++++++++--- .../intrinsics/vstrwq_scatter_base_wb_u32.c | 32 ++++++++++++--- .../intrinsics/vstrwq_scatter_offset_f32.c | 32 ++++++++++++--- .../intrinsics/vstrwq_scatter_offset_p_f32.c | 40 ++++++++++++++++--- .../intrinsics/vstrwq_scatter_offset_p_s32.c | 40 ++++++++++++++++--- .../intrinsics/vstrwq_scatter_offset_p_u32.c | 40 ++++++++++++++++--- .../intrinsics/vstrwq_scatter_offset_s32.c | 32 ++++++++++++--- .../intrinsics/vstrwq_scatter_offset_u32.c | 32 ++++++++++++--- .../vstrwq_scatter_shifted_offset_f32.c | 32 ++++++++++++--- .../vstrwq_scatter_shifted_offset_p_f32.c | 40 ++++++++++++++++--- .../vstrwq_scatter_shifted_offset_p_s32.c | 40 ++++++++++++++++--- .../vstrwq_scatter_shifted_offset_p_u32.c | 40 ++++++++++++++++--- .../vstrwq_scatter_shifted_offset_s32.c | 32 ++++++++++++--- .../vstrwq_scatter_shifted_offset_u32.c | 32 ++++++++++++--- .../arm/mve/intrinsics/vstrwq_u32.c | 32 ++++++++++++--- 33 files changed, 922 insertions(+), 178 deletions(-) diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 504cd938b26..05a4ebbdd67 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -102,10 +102,6 @@ (define_constraint "Rg" (match_test "TARGET_HAVE_MVE && ((ival == 1) || (ival == 2) || (ival == 4) || (ival == 8))"))) -;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE. -(define_predicate "mve_vldrd_immediate" - (match_test "satisfies_constraint_Ri (op)")) - (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS" "The VFP registers @code{s0}-@code{s31}.") @@ -574,6 +570,22 @@ (define_constraint "US" (match_code "symbol_ref") ) +;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE. +(define_constraint "Ri" + "@internal In Thumb-2 state a constant is multiple of 8 and in range + of -/+ 1016 for MVE" + (and (match_code "const_int") + (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016) + && ((ival % 8) == 0)"))) + +;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE. +(define_constraint "Rl" + "@internal In Thumb-2 state a constant is multiple of 2 and in range + of -/+ 252 for MVE" + (and (match_code "const_int") + (match_test "TARGET_HAVE_MVE && (-252 <= ival) && (ival <= 252) + && ((ival % 2) == 0)"))) + (define_memory_constraint "Uz" "@internal A memory access that is accessible as an LDC/STC operand" diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 35eab6c94bf..161794e470c 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -9359,7 +9359,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_v4si" [(match_operand:V4SI 1 "s_register_operand" "0") (match_operand:SI 2 "mve_vldrd_immediate" "Ri") (match_operand:V4SI 3 "s_register_operand" "w") - (match_operand:V4BI 4 "vpr_register_operand")] + (match_operand:V4BI 4 "vpr_register_operand" "Up")] VSTRWSBWBQ)) (set (match_operand:V4SI 0 "s_register_operand" "=w") (unspec:V4SI [(match_dup 1) (match_dup 2)] @@ -9408,9 +9408,9 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf" [(set (mem:BLK (scratch)) (unspec:BLK [(match_operand:V4SI 1 "s_register_operand" "0") - (match_operand:SI 2 "mve_vldrd_immediate" "Ri") + (match_operand:SI 2 "mve_vstrw_immediate" "Rl") (match_operand:V4SF 3 "s_register_operand" "w") - (match_operand:V4BI 4 "vpr_register_operand")] + (match_operand:V4BI 4 "vpr_register_operand" "Up")] VSTRWQSBWB_F)) (set (match_operand:V4SI 0 "s_register_operand" "=w") (unspec:V4SI [(match_dup 1) (match_dup 2)] @@ -9422,7 +9422,7 @@ (define_insn "mve_vstrwq_scatter_base_wb_p_fv4sf" ops[0] = operands[1]; ops[1] = operands[2]; ops[2] = operands[3]; - output_asm_insn ("vpst\;\tvstrwt.u32\t%q2, [%q0, %1]!",ops); + output_asm_insn ("vpst\;vstrwt.u32\t%q2, [%q0, %1]!",ops); return ""; } [(set_attr "length" "8")]) @@ -9461,7 +9461,7 @@ (define_insn "mve_vstrdq_scatter_base_wb_p_v2di" [(match_operand:V2DI 1 "s_register_operand" "0") (match_operand:SI 2 "mve_vldrd_immediate" "Ri") (match_operand:V2DI 3 "s_register_operand" "w") - (match_operand:V2QI 4 "vpr_register_operand")] + (match_operand:V2QI 4 "vpr_register_operand" "Up")] VSTRDSBWBQ)) (set (match_operand:V2DI 0 "s_register_operand" "=w") (unspec:V2DI [(match_dup 1) (match_dup 2)] diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 3139750c606..00995a590ab 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -73,13 +73,13 @@ (define_predicate "mve_imm_32" (define_predicate "mve_imm_selective_upto_8" (match_test "satisfies_constraint_Rg (op)")) -;; True if the immediate is the range +/- 1016 and multiple of 8 for MVE. -(define_constraint "Ri" - "@internal In Thumb-2 state a constant is multiple of 8 and in range - of -/+ 1016 for MVE" - (and (match_code "const_int") - (match_test "TARGET_HAVE_MVE && (-1016 <= ival) && (ival <= 1016) - && ((ival % 8) == 0)"))) +;; True if the immediate is multiple of 8 and in range of -/+ 1016 for MVE. +(define_predicate "mve_vldrd_immediate" + (match_test "satisfies_constraint_Ri (op)")) + +;; True if the immediate is multiple of 2 and in range of -/+ 252 for MVE. +(define_predicate "mve_vstrw_immediate" + (match_test "satisfies_constraint_Rl (op)")) ; Predicate for stack protector guard's address in ; stack_protect_combined_set_insn and stack_protect_combined_test_insn patterns diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c index 8aa04fcbdee..e92ecb0f6bc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (float32_t * addr, float32x4_t value) +foo (float32_t *base, float32x4_t value) { - vstrwq_f32 (addr, value); + return vstrwq_f32 (base, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (float32_t * addr, float32x4_t value) +foo1 (float32_t *base, float32x4_t value) { - vstrwq (addr, value); + return vstrwq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c index 411de6414f7..f1992a67736 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (float32_t * addr, float32x4_t value, mve_pred16_t p) +foo (float32_t *base, float32x4_t value, mve_pred16_t p) { - vstrwq_p_f32 (addr, value, p); + return vstrwq_p_f32 (base, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (float32_t * addr, float32x4_t value, mve_pred16_t p) +foo1 (float32_t *base, float32x4_t value, mve_pred16_t p) { - vstrwq_p (addr, value, p); + return vstrwq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c index 3b042814d27..a00aeabb9fe 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int32_t * addr, int32x4_t value, mve_pred16_t p) +foo (int32_t *base, int32x4_t value, mve_pred16_t p) { - vstrwq_p_s32 (addr, value, p); + return vstrwq_p_s32 (base, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int32_t * addr, int32x4_t value, mve_pred16_t p) +foo1 (int32_t *base, int32x4_t value, mve_pred16_t p) { - vstrwq_p (addr, value, p); + return vstrwq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c index b9e92204c88..05fded8aac8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint32_t * addr, uint32x4_t value, mve_pred16_t p) +foo (uint32_t *base, uint32x4_t value, mve_pred16_t p) { - vstrwq_p_u32 (addr, value, p); + return vstrwq_p_u32 (base, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint32_t * addr, uint32x4_t value, mve_pred16_t p) +foo1 (uint32_t *base, uint32x4_t value, mve_pred16_t p) { - vstrwq_p (addr, value, p); + return vstrwq_p (base, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c index c7b3d91a972..b2a184f3c66 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (int32_t * addr, int32x4_t value) +foo (int32_t *base, int32x4_t value) { - vstrwq_s32 (addr, value); + return vstrwq_s32 (base, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (int32_t * addr, int32x4_t value) +foo1 (int32_t *base, int32x4_t value) { - vstrwq (addr, value); + return vstrwq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c index f8b56917295..c80e8d9cdc5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo (uint32x4_t addr, float32x4_t value) { - vstrwq_scatter_base_f32 (addr, 8, value); + return vstrwq_scatter_base_f32 (addr, 0, value); } -/* { dg-final { scan-assembler "vstrw.u32" } } */ +/* +**foo1: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo1 (uint32x4_t addr, float32x4_t value) { - vstrwq_scatter_base (addr, 8, value); + return vstrwq_scatter_base (addr, 0, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c index 4a75e6503e1..237843c0661 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo (uint32x4_t addr, float32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_p_f32 (addr, 8, value, p); + return vstrwq_scatter_base_p_f32 (addr, 0, value, p); } -/* { dg-final { scan-assembler "vstrwt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo1 (uint32x4_t addr, float32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_p (addr, 8, value, p); + return vstrwq_scatter_base_p (addr, 0, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c index 5ac4f300a7d..5f4f4a09664 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo (uint32x4_t addr, int32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_p_s32 (addr, 8, value, p); + return vstrwq_scatter_base_p_s32 (addr, 0, value, p); } -/* { dg-final { scan-assembler "vstrwt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo1 (uint32x4_t addr, int32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_p (addr, 8, value, p); + return vstrwq_scatter_base_p (addr, 0, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c index e564f26b9c7..8c5cf63f861 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo (uint32x4_t addr, uint32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_p_u32 (addr, 8, value, p); + return vstrwq_scatter_base_p_u32 (addr, 0, value, p); } -/* { dg-final { scan-assembler "vstrwt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo1 (uint32x4_t addr, uint32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_p (addr, 8, value, p); + return vstrwq_scatter_base_p (addr, 0, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c index 5bba36db5cb..5208cf4f808 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo (uint32x4_t addr, int32x4_t value) { - vstrwq_scatter_base_s32 (addr, 8, value); + return vstrwq_scatter_base_s32 (addr, 0, value); } -/* { dg-final { scan-assembler "vstrw.u32" } } */ +/* +**foo1: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo1 (uint32x4_t addr, int32x4_t value) { - vstrwq_scatter_base (addr, 8, value); + return vstrwq_scatter_base (addr, 0, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c index 1dcbb5a739c..e728db2b9f1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo (uint32x4_t addr, uint32x4_t value) { - vstrwq_scatter_base_u32 (addr, 8, value); + return vstrwq_scatter_base_u32 (addr, 0, value); } -/* { dg-final { scan-assembler "vstrw.u32" } } */ +/* +**foo1: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\](?: @.*|) +** ... +*/ void foo1 (uint32x4_t addr, uint32x4_t value) { - vstrwq_scatter_base (addr, 8, value); + return vstrwq_scatter_base (addr, 0, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c index b2cc6e555ae..e481191aa57 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_f32.c @@ -1,19 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo (uint32x4_t * addr, const int offset, float32x4_t value) +foo (uint32x4_t *addr, float32x4_t value) { - vstrwq_scatter_base_wb_f32 (addr, 8, value); + return vstrwq_scatter_base_wb_f32 (addr, 0, value); } + +/* +**foo1: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo1 (uint32x4_t * addr, const int offset, float32x4_t value) +foo1 (uint32x4_t *addr, float32x4_t value) { - vstrwq_scatter_base_wb (addr, 8, value); + return vstrwq_scatter_base_wb (addr, 0, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c index 4befd49d7b9..8d217d46230 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c @@ -1,19 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p) +foo (uint32x4_t *addr, float32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_wb_p_f32 (addr, 8, value, p); + return vstrwq_scatter_base_wb_p_f32 (addr, 0, value, p); } + +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo1 (uint32x4_t * addr, const int offset, float32x4_t value, mve_pred16_t p) +foo1 (uint32x4_t *addr, float32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_wb_p (addr, 8, value, p); + return vstrwq_scatter_base_wb_p (addr, 0, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c index dfb1827c4f0..afc47adcd7f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c @@ -1,19 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p) +foo (uint32x4_t *addr, int32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_wb_p_s32 (addr, 8, value, p); + return vstrwq_scatter_base_wb_p_s32 (addr, 0, value, p); } + +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo1 (uint32x4_t * addr, const int offset, int32x4_t value, mve_pred16_t p) +foo1 (uint32x4_t *addr, int32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_wb_p (addr, 8, value, p); + return vstrwq_scatter_base_wb_p (addr, 0, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c index 4eb78c600be..65191c2f1ed 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c @@ -1,19 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p) +foo (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_wb_p_u32 (addr, 8, value, p); + return vstrwq_scatter_base_wb_p_u32 (addr, 0, value, p); } + +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo1 (uint32x4_t * addr, const int offset, uint32x4_t value, mve_pred16_t p) +foo1 (uint32x4_t *addr, uint32x4_t value, mve_pred16_t p) { - vstrwq_scatter_base_wb_p (addr, 8, value, p); + return vstrwq_scatter_base_wb_p (addr, 0, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler-times "vstrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c index 618dbaf5aa6..b6a9f6cd1f4 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_s32.c @@ -1,19 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo (uint32x4_t * addr, const int offset, int32x4_t value) +foo (uint32x4_t *addr, int32x4_t value) { - vstrwq_scatter_base_wb_s32 (addr, 8, value); + return vstrwq_scatter_base_wb_s32 (addr, 0, value); } + +/* +**foo1: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo1 (uint32x4_t * addr, const int offset, int32x4_t value) +foo1 (uint32x4_t *addr, int32x4_t value) { - vstrwq_scatter_base_wb (addr, 8, value); + return vstrwq_scatter_base_wb (addr, 0, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c index 912a4590cf5..81a278f4e2b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base_wb_u32.c @@ -1,19 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo (uint32x4_t * addr, uint32x4_t value) +foo (uint32x4_t *addr, uint32x4_t value) { - vstrwq_scatter_base_wb_u32 (addr, 8, value); + return vstrwq_scatter_base_wb_u32 (addr, 0, value); } + +/* +**foo1: +** ... +** vstrw.u32 q[0-9]+, \[q[0-9]+, #[0-9]+\]!(?: @.*|) +** ... +*/ void -foo1 (uint32x4_t * addr, uint32x4_t value) +foo1 (uint32x4_t *addr, uint32x4_t value) { - vstrwq_scatter_base_wb (addr, 8, value); + return vstrwq_scatter_base_wb (addr, 0, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler-times "vstrw.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" 2 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c index c14d3ce607b..b81df68aa21 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (float32_t * base, uint32x4_t offset, float32x4_t value) +foo (float32_t *base, uint32x4_t offset, float32x4_t value) { - vstrwq_scatter_offset_f32 (base, offset, value); + return vstrwq_scatter_offset_f32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value) +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value) { - vstrwq_scatter_offset (base, offset, value); + return vstrwq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c index 115be56ec00..8aee42f76a3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_f32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) +foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) { - vstrwq_scatter_offset_p_f32 (base, offset, value, p); + return vstrwq_scatter_offset_p_f32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) { - vstrwq_scatter_offset_p (base, offset, value, p); + return vstrwq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c index 48652af3cff..9c74ae7a8d8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) { - vstrwq_scatter_offset_p_s32 (base, offset, value, p); + return vstrwq_scatter_offset_p_s32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) { - vstrwq_scatter_offset_p (base, offset, value, p); + return vstrwq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c index dcd42ec453f..015a202b548 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_p_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) { - vstrwq_scatter_offset_p_u32 (base, offset, value, p); + return vstrwq_scatter_offset_p_u32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) { - vstrwq_scatter_offset_p (base, offset, value, p); + return vstrwq_scatter_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c index 04672e5a4aa..df373111b78 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (int32_t * base, uint32x4_t offset, int32x4_t value) +foo (int32_t *base, uint32x4_t offset, int32x4_t value) { - vstrwq_scatter_offset_s32 (base, offset, value); + return vstrwq_scatter_offset_s32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value) +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value) { - vstrwq_scatter_offset (base, offset, value); + return vstrwq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c index e3d312550c6..a74696ca273 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_offset_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value) +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value) { - vstrwq_scatter_offset_u32 (base, offset, value); + return vstrwq_scatter_offset_u32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+\](?: @.*|) +** ... +*/ void -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value) +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value) { - vstrwq_scatter_offset (base, offset, value); + return vstrwq_scatter_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c index b20c4c7ed3a..1c9b29a57b8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_f32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo (float32_t * base, uint32x4_t offset, float32x4_t value) +foo (float32_t *base, uint32x4_t offset, float32x4_t value) { - vstrwq_scatter_shifted_offset_f32 (base, offset, value); + return vstrwq_scatter_shifted_offset_f32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value) +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value) { - vstrwq_scatter_shifted_offset (base, offset, value); + return vstrwq_scatter_shifted_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c index 1682f702dc6..08e1572854e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_f32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) +foo (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) { - vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p); + return vstrwq_scatter_shifted_offset_p_f32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo1 (float32_t * base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) +foo1 (float32_t *base, uint32x4_t offset, float32x4_t value, mve_pred16_t p) { - vstrwq_scatter_shifted_offset_p (base, offset, value, p); + return vstrwq_scatter_shifted_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c index eef6ea6e196..2b8f8a7d61f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_s32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +foo (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) { - vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p); + return vstrwq_scatter_shifted_offset_p_s32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value, mve_pred16_t p) { - vstrwq_scatter_shifted_offset_p (base, offset, value, p); + return vstrwq_scatter_shifted_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c index b11e7e04dc4..3e4e87bf79a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_p_u32.c @@ -1,21 +1,49 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) { - vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p); + return vstrwq_scatter_shifted_offset_p_u32 (base, offset, value, p); } -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vstrwt.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value, mve_pred16_t p) { - vstrwq_scatter_shifted_offset_p (base, offset, value, p); + return vstrwq_scatter_shifted_offset_p (base, offset, value, p); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrwt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c index 8ac25c47554..7f25490a69a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_s32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo (int32_t * base, uint32x4_t offset, int32x4_t value) +foo (int32_t *base, uint32x4_t offset, int32x4_t value) { - vstrwq_scatter_shifted_offset_s32 (base, offset, value); + return vstrwq_scatter_shifted_offset_s32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo1 (int32_t * base, uint32x4_t offset, int32x4_t value) +foo1 (int32_t *base, uint32x4_t offset, int32x4_t value) { - vstrwq_scatter_shifted_offset (base, offset, value); + return vstrwq_scatter_shifted_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c index 1ce0ddacc7a..a96220c4f6e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_shifted_offset_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo (uint32_t * base, uint32x4_t offset, uint32x4_t value) +foo (uint32_t *base, uint32x4_t offset, uint32x4_t value) { - vstrwq_scatter_shifted_offset_u32 (base, offset, value); + return vstrwq_scatter_shifted_offset_u32 (base, offset, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+), q[0-9]+, uxtw #2\](?: @.*|) +** ... +*/ void -foo1 (uint32_t * base, uint32x4_t offset, uint32x4_t value) +foo1 (uint32_t *base, uint32x4_t offset, uint32x4_t value) { - vstrwq_scatter_shifted_offset (base, offset, value); + return vstrwq_scatter_shifted_offset (base, offset, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c index 4aec9935b84..df554af79a6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_u32.c @@ -1,21 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* +**foo: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo (uint32_t * addr, uint32x4_t value) +foo (uint32_t *base, uint32x4_t value) { - vstrwq_u32 (addr, value); + return vstrwq_u32 (base, value); } -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* +**foo1: +** ... +** vstrw.32 q[0-9]+, \[(?:ip|fp|r[0-9]+)\](?: @.*|) +** ... +*/ void -foo1 (uint32_t * addr, uint32x4_t value) +foo1 (uint32_t *base, uint32x4_t value) { - vstrwq (addr, value); + return vstrwq (base, value); +} + +#ifdef __cplusplus } +#endif -/* { dg-final { scan-assembler "vstrw.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */