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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id x20-20020aa7d394000000b00504803f4071sm8669431edq.44.2023.04.27.23.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 23:12:26 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 09/11] riscv: thead: Factor out XThead*-specific peepholes Date: Fri, 28 Apr 2023 08:12:10 +0200 Message-Id: <20230428061210.2988035-10-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230428061210.2988035-1-christoph.muellner@vrull.eu> References: <20230428061210.2988035-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764399618915886515?= X-GMAIL-MSGID: =?utf-8?q?1764399618915886515?= From: Christoph Müllner This patch moves the XThead*-specific peephole passes into thead-peephole.md with the intend to keep vendor-specific code separated from RISC-V standard code. This patch does not contain any functional changes. gcc/ChangeLog: * config/riscv/peephole.md: Remove XThead* peephole passes. * config/riscv/thead.md: Include thead-peephole.md. * config/riscv/thead-peephole.md: New file. Signed-off-by: Christoph Müllner --- gcc/config/riscv/peephole.md | 56 ---------------------- gcc/config/riscv/thead-peephole.md | 74 ++++++++++++++++++++++++++++++ gcc/config/riscv/thead.md | 2 + 3 files changed, 76 insertions(+), 56 deletions(-) create mode 100644 gcc/config/riscv/thead-peephole.md diff --git a/gcc/config/riscv/peephole.md b/gcc/config/riscv/peephole.md index 67e7046d7e6..0ef0c04410b 100644 --- a/gcc/config/riscv/peephole.md +++ b/gcc/config/riscv/peephole.md @@ -38,59 +38,3 @@ (define_peephole2 { operands[5] = GEN_INT (INTVAL (operands[2]) - INTVAL (operands[5])); }) - -;; XTheadMemPair: merge two SI or DI loads -(define_peephole2 - [(set (match_operand:GPR 0 "register_operand" "") - (match_operand:GPR 1 "memory_operand" "")) - (set (match_operand:GPR 2 "register_operand" "") - (match_operand:GPR 3 "memory_operand" ""))] - "TARGET_XTHEADMEMPAIR - && th_mempair_operands_p (operands, true, mode)" - [(parallel [(set (match_dup 0) (match_dup 1)) - (set (match_dup 2) (match_dup 3))])] -{ - th_mempair_order_operands (operands, true, mode); -}) - -;; XTheadMemPair: merge two SI or DI stores -(define_peephole2 - [(set (match_operand:GPR 0 "memory_operand" "") - (match_operand:GPR 1 "register_operand" "")) - (set (match_operand:GPR 2 "memory_operand" "") - (match_operand:GPR 3 "register_operand" ""))] - "TARGET_XTHEADMEMPAIR - && th_mempair_operands_p (operands, false, mode)" - [(parallel [(set (match_dup 0) (match_dup 1)) - (set (match_dup 2) (match_dup 3))])] -{ - th_mempair_order_operands (operands, false, mode); -}) - -;; XTheadMemPair: merge two SI loads with sign-extension -(define_peephole2 - [(set (match_operand:DI 0 "register_operand" "") - (sign_extend:DI (match_operand:SI 1 "memory_operand" ""))) - (set (match_operand:DI 2 "register_operand" "") - (sign_extend:DI (match_operand:SI 3 "memory_operand" "")))] - "TARGET_XTHEADMEMPAIR && TARGET_64BIT - && th_mempair_operands_p (operands, true, SImode)" - [(parallel [(set (match_dup 0) (sign_extend:DI (match_dup 1))) - (set (match_dup 2) (sign_extend:DI (match_dup 3)))])] -{ - th_mempair_order_operands (operands, true, SImode); -}) - -;; XTheadMemPair: merge two SI loads with zero-extension -(define_peephole2 - [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (match_operand:SI 1 "memory_operand" ""))) - (set (match_operand:DI 2 "register_operand" "") - (zero_extend:DI (match_operand:SI 3 "memory_operand" "")))] - "TARGET_XTHEADMEMPAIR && TARGET_64BIT - && th_mempair_operands_p (operands, true, SImode)" - [(parallel [(set (match_dup 0) (zero_extend:DI (match_dup 1))) - (set (match_dup 2) (zero_extend:DI (match_dup 3)))])] -{ - th_mempair_order_operands (operands, true, SImode); -}) diff --git a/gcc/config/riscv/thead-peephole.md b/gcc/config/riscv/thead-peephole.md new file mode 100644 index 00000000000..5b829b5b968 --- /dev/null +++ b/gcc/config/riscv/thead-peephole.md @@ -0,0 +1,74 @@ +;; Machine description for T-Head vendor extensions +;; Copyright (C) 2023 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; XTheadMemPair: merge two SI or DI loads +(define_peephole2 + [(set (match_operand:GPR 0 "register_operand" "") + (match_operand:GPR 1 "memory_operand" "")) + (set (match_operand:GPR 2 "register_operand" "") + (match_operand:GPR 3 "memory_operand" ""))] + "TARGET_XTHEADMEMPAIR + && th_mempair_operands_p (operands, true, mode)" + [(parallel [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) (match_dup 3))])] +{ + th_mempair_order_operands (operands, true, mode); +}) + +;; XTheadMemPair: merge two SI or DI stores +(define_peephole2 + [(set (match_operand:GPR 0 "memory_operand" "") + (match_operand:GPR 1 "register_operand" "")) + (set (match_operand:GPR 2 "memory_operand" "") + (match_operand:GPR 3 "register_operand" ""))] + "TARGET_XTHEADMEMPAIR + && th_mempair_operands_p (operands, false, mode)" + [(parallel [(set (match_dup 0) (match_dup 1)) + (set (match_dup 2) (match_dup 3))])] +{ + th_mempair_order_operands (operands, false, mode); +}) + +;; XTheadMemPair: merge two SI loads with sign-extension +(define_peephole2 + [(set (match_operand:DI 0 "register_operand" "") + (sign_extend:DI (match_operand:SI 1 "memory_operand" ""))) + (set (match_operand:DI 2 "register_operand" "") + (sign_extend:DI (match_operand:SI 3 "memory_operand" "")))] + "TARGET_XTHEADMEMPAIR && TARGET_64BIT + && th_mempair_operands_p (operands, true, SImode)" + [(parallel [(set (match_dup 0) (sign_extend:DI (match_dup 1))) + (set (match_dup 2) (sign_extend:DI (match_dup 3)))])] +{ + th_mempair_order_operands (operands, true, SImode); +}) + +;; XTheadMemPair: merge two SI loads with zero-extension +(define_peephole2 + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:DI (match_operand:SI 1 "memory_operand" ""))) + (set (match_operand:DI 2 "register_operand" "") + (zero_extend:DI (match_operand:SI 3 "memory_operand" "")))] + "TARGET_XTHEADMEMPAIR && TARGET_64BIT + && th_mempair_operands_p (operands, true, SImode)" + [(parallel [(set (match_dup 0) (zero_extend:DI (match_dup 1))) + (set (match_dup 2) (zero_extend:DI (match_dup 3)))])] +{ + th_mempair_order_operands (operands, true, SImode); +}) diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index aa933960a98..1ac4dd9b462 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -374,3 +374,5 @@ (define_insn "*th_mempair_load_zero_extendsidi2" [(set_attr "move_type" "load") (set_attr "mode" "DI") (set_attr "length" "8")]) + +(include "thead-peephole.md")