From patchwork Fri Apr 28 02:21:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Die Li X-Patchwork-Id: 88434 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp652968vqo; Thu, 27 Apr 2023 19:22:21 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6ybhOi0+S+Yo7THD1G+yqTQpR8DJgm8DwwZoMfApfZGg0soDOTMvPurFkROQRal5YAB8AU X-Received: by 2002:a17:906:dac8:b0:94f:123:fb83 with SMTP id xi8-20020a170906dac800b0094f0123fb83mr3256319ejb.73.1682648541146; Thu, 27 Apr 2023 19:22:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682648541; cv=none; d=google.com; s=arc-20160816; b=cMALwcM+go3mks94de6Vt+g4zaQU9fT2NaxRgfARJtF0xSnIIiNp3WeJgg4fqxLTDy ImcK5jvsbAN/tmR5L/O5CbDIRMcZ0n47ApeRtkl1J6BEbuzss+g4cPiHTHaiD5j5LM4F VYP63Q/jIHWUmeOsh5YpraY9Zs1RXwFNQF07iwJzD/3dapHpakbQMRaMvrgLJln1NasW oYs2DTM4J9Nfxq31W5wHGz9BTD4NflNb5CWNA4ev3WycmgwNeVSjDQADdDtD1pwP/yXy clGX9pajwN6K5Y/mD09bgOEl8N+U0BCMynAqmbWqlAOu5hCNAsvqI1JWTisz31tAR9zD /sWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:message-id:date:subject:cc:to :from:dmarc-filter:delivered-to; bh=MjQ8xc0UqKpu4kuyuiccLznTg+abAwKjQkVEEl2ubIA=; b=rA7XMY0v6YjV17hGtwpKcQRKlMPnEBYjNRB3rsPg4cHYtOcOc+IC8+syIvMivXSZYO 5ov/mwFSiA5BGyRkOjrDrn3pwpkvTgEpXMD5/RHNDEHe1CJpOpuqm1qNc+8VUKLFS6qU qdX9qkP7gKxgEu/x2QQaZfZAMVlwcREN8rNMcztrFbmPcrlau125fv9iVQLwqBewLg0G v+k7eayZA8D0nEVRZ+POqSsA2AfLUnUILSYrA2CxBbuiHjzjghiT5s17UMTG22IreLlS FVnLMyJ58czR91ebGJvsrSloV8yZDXZDGe4f+D7NVGZNifAY/BeFqsM/e4wC0LfUyXy9 RvSg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id ju8-20020a17090798a800b0094f360fd128si13926719ejc.333.2023.04.27.19.22.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 19:22:21 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3F0D13857707 for ; Fri, 28 Apr 2023 02:22:16 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from azure-sdnproxy.icoremail.net (azure-sdnproxy.icoremail.net [207.46.229.174]) by sourceware.org (Postfix) with ESMTP id DCFAB3858C1F for ; Fri, 28 Apr 2023 02:21:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DCFAB3858C1F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from host040-ubuntu-1804.lxd (unknown [10.12.130.38]) by app1 (Coremail) with SMTP id EwgMCgC3VMS3LUtka6YOAA--.35499S4; Fri, 28 Apr 2023 10:21:44 +0800 (CST) From: Die Li To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, gaofei@eswincomputing.com, Die Li Subject: [PATCH] [RISC-V] Fix riscv_expand_conditional_move. Date: Fri, 28 Apr 2023 02:21:41 +0000 Message-Id: <20230428022141.2080-1-lidie@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: EwgMCgC3VMS3LUtka6YOAA--.35499S4 X-Coremail-Antispam: 1UD129KBjvJXoW3GFyrWF4UGr17KryfJr4kCrg_yoW3XFy5pF 43GrWIvwnrJa43CFn3tF43AF1Yk3Wrtr4Fv3srXFya9rWUJ395Jryvk342qw1fJr9xurZ3 CanrKrs7Cr4DZ37anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK6svPMxAI w28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr 4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxG rwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8Jw CI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2 z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUoOJ5UUUUU X-CM-SenderInfo: 5olgxv46hv4xpqfrz1xxwl0woofrz/ X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764384876251938081?= X-GMAIL-MSGID: =?utf-8?q?1764384876251938081?= Two issues have been observed in current riscv_expand_conditional_move implementation. 1. Before introduction of TARGET_XTHEADCONDMOV, op0 of comparision expression is used for mode comparision with word_mode, but after TARGET_XTHEADCONDMOV megered with TARGET_SFB_ALU, dest of if-then-else is used for mode comparision with word_mode, and from md file mode of dest is DI or SI which can be different with word_mode in RV64. 2. TARGET_XTHEADCONDMOV cannot be generated when the mode of the comparison is E_VOID. This patch solves the issues above. Provide an example from the newly added test case. Testcase: int ConNmv_reg_reg_reg(int x, int y, int z, int n){ if (x != y) return z; return n; } Cflags: -O2 -march=rv64gc_xtheadcondmov -mabi=lp64d before patch: ConNmv_reg_reg_reg: bne a0,a1,.L23 mv a2,a3 .L23: mv a0,a2 ret after patch: ConNmv_reg_reg_reg: sub a1,a0,a1 th.mveqz a2,zero,a1 th.mvnez a3,zero,a1 or a0,a2,a3 ret Co-Authored by: Fei Gao Signed-off-by: Die Li gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_conditional_move): Fix mode checking. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadcondmov-indirect-rv32.c: New test. * gcc.target/riscv/xtheadcondmov-indirect-rv64.c: New test. --- gcc/config/riscv/riscv.cc | 4 +- .../riscv/xtheadcondmov-indirect-rv32.c | 116 ++++++++++++++++++ .../riscv/xtheadcondmov-indirect-rv64.c | 116 ++++++++++++++++++ 3 files changed, 234 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 1529855a2b4..30ace45dc5f 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3411,7 +3411,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) && GET_MODE_CLASS (mode) == MODE_INT && reg_or_0_operand (cons, mode) && reg_or_0_operand (alt, mode) - && GET_MODE (op) == mode + && (GET_MODE (op) == mode || GET_MODE (op) == E_VOIDmode) && GET_MODE (op0) == mode && GET_MODE (op1) == mode && (code == EQ || code == NE)) @@ -3420,7 +3420,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt) return true; } else if (TARGET_SFB_ALU - && mode == word_mode) + && GET_MODE (op0) == word_mode) { riscv_emit_int_compare (&code, &op0, &op1); rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c new file mode 100644 index 00000000000..9afdc2eabfd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c @@ -0,0 +1,116 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_xtheadcondmov -mabi=ilp32 -mriscv-attribute" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +**ConEmv_imm_imm_reg: +** addi a5,a0,-1000 +** li a0,10 +** th.mvnez a0,zero,a5 +** th.mveqz a1,zero,a5 +** or a0,a0,a1 +** ret +*/ +int ConEmv_imm_imm_reg(int x, int y){ + if (x == 1000) return 10; + return y; +} + +/* +**ConEmv_imm_reg_reg: +** addi a5,a0,-1000 +** th.mvnez a1,zero,a5 +** th.mveqz a2,zero,a5 +** or a0,a1,a2 +** ret +*/ +int ConEmv_imm_reg_reg(int x, int y, int z){ + if (x == 1000) return y; + return z; +} + +/* +**ConEmv_reg_imm_reg: +** sub a1,a0,a1 +** li a0,10 +** th.mvnez a0,zero,a1 +** th.mveqz a2,zero,a1 +** or a0,a0,a2 +** ret +*/ +int ConEmv_reg_imm_reg(int x, int y, int z){ + if (x == y) return 10; + return z; +} + +/* +**ConEmv_reg_reg_reg: +** sub a1,a0,a1 +** th.mvnez a2,zero,a1 +** th.mveqz a3,zero,a1 +** or a0,a2,a3 +** ret +*/ +int ConEmv_reg_reg_reg(int x, int y, int z, int n){ + if (x == y) return z; + return n; +} + +/* +**ConNmv_imm_imm_reg: +** li a5,9998336 +** addi a4,a0,-1000 +** addi a5,a5,1664 +** th.mvnez a1,zero,a4 +** th.mveqz a5,zero,a4 +** or a0,a1,a5 +** ret +*/ +int ConNmv_imm_imm_reg(int x, int y){ + if (x != 1000) return 10000000; + return y; +} + +/* +**ConNmv_imm_reg_reg: +** addi a5,a0,-1000 +** th.mveqz a1,zero,a5 +** th.mvnez a2,zero,a5 +** or a0,a1,a2 +** ret +*/ +int ConNmv_imm_reg_reg(int x, int y, int z){ + if (x != 1000) return y; + return z; +} + +/* +**ConNmv_reg_imm_reg: +** sub a1,a0,a1 +** li a0,10 +** th.mveqz a0,zero,a1 +** th.mvnez a2,zero,a1 +** or a0,a0,a2 +** ret +*/ +int ConNmv_reg_imm_reg(int x, int y, int z){ + if (x != y) return 10; + return z; +} + +/* +**ConNmv_reg_reg_reg: +** sub a1,a0,a1 +** th.mveqz a2,zero,a1 +** th.mvnez a3,zero,a1 +** or a0,a2,a3 +** ret +*/ +int ConNmv_reg_reg_reg(int x, int y, int z, int n){ + if (x != y) return z; + return n; +} + + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_xtheadcondmov1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c new file mode 100644 index 00000000000..a1982fd90bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c @@ -0,0 +1,116 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_xtheadcondmov -mabi=lp64d -mriscv-attribute" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +/* +**ConEmv_imm_imm_reg: +** addi a5,a0,-1000 +** li a0,10 +** th.mvnez a0,zero,a5 +** th.mveqz a1,zero,a5 +** or a0,a0,a1 +** ret +*/ +int ConEmv_imm_imm_reg(int x, int y){ + if (x == 1000) return 10; + return y; +} + +/* +**ConEmv_imm_reg_reg: +** addi a5,a0,-1000 +** th.mvnez a1,zero,a5 +** th.mveqz a2,zero,a5 +** or a0,a1,a2 +** ret +*/ +int ConEmv_imm_reg_reg(int x, int y, int z){ + if (x == 1000) return y; + return z; +} + +/* +**ConEmv_reg_imm_reg: +** sub a1,a0,a1 +** li a0,10 +** th.mvnez a0,zero,a1 +** th.mveqz a2,zero,a1 +** or a0,a0,a2 +** ret +*/ +int ConEmv_reg_imm_reg(int x, int y, int z){ + if (x == y) return 10; + return z; +} + +/* +**ConEmv_reg_reg_reg: +** sub a1,a0,a1 +** th.mvnez a2,zero,a1 +** th.mveqz a3,zero,a1 +** or a0,a2,a3 +** ret +*/ +int ConEmv_reg_reg_reg(int x, int y, int z, int n){ + if (x == y) return z; + return n; +} + +/* +**ConNmv_imm_imm_reg: +** li a5,9998336 +** addi a4,a0,-1000 +** addi a5,a5,1664 +** th.mvnez a1,zero,a4 +** th.mveqz a5,zero,a4 +** or a0,a1,a5 +** ret +*/ +int ConNmv_imm_imm_reg(int x, int y){ + if (x != 1000) return 10000000; + return y; +} + +/* +**ConNmv_imm_reg_reg: +** addi a5,a0,-1000 +** th.mveqz a1,zero,a5 +** th.mvnez a2,zero,a5 +** or a0,a1,a2 +** ret +*/ +int ConNmv_imm_reg_reg(int x, int y, int z){ + if (x != 1000) return y; + return z; +} + +/* +**ConNmv_reg_imm_reg: +** sub a1,a0,a1 +** li a0,10 +** th.mveqz a0,zero,a1 +** th.mvnez a2,zero,a1 +** or a0,a0,a2 +** ret +*/ +int ConNmv_reg_imm_reg(int x, int y, int z){ + if (x != y) return 10; + return z; +} + +/* +**ConNmv_reg_reg_reg: +** sub a1,a0,a1 +** th.mveqz a2,zero,a1 +** th.mvnez a3,zero,a1 +** or a0,a2,a3 +** ret +*/ +int ConNmv_reg_reg_reg(int x, int y, int z, int n){ + if (x != y) return z; + return n; +} + + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_xtheadcondmov1p0\"" } } */