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[8.43.85.97]) by mx.google.com with ESMTPS id j16-20020a50ed10000000b00506b1acb507si9782115eds.464.2023.04.27.09.29.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 09:29:16 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=0XsE7Kxs; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C20BA38A8157 for ; Thu, 27 Apr 2023 16:25:24 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x644.google.com (mail-pl1-x644.google.com [IPv6:2607:f8b0:4864:20::644]) by sourceware.org (Postfix) with ESMTPS id C3F2A385770B for ; Thu, 27 Apr 2023 16:24:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C3F2A385770B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x644.google.com with SMTP id d9443c01a7336-1a68d61579bso65780705ad.1 for ; Thu, 27 Apr 2023 09:24:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1682612660; x=1685204660; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jj5QT1yI1Yn4DschSmlhYBQXITm427STmY5/fgnqXfU=; b=0XsE7Kxs3Jwza7XDCgGpc3/ioCdgNjwPvj8KladszLxwCkDedFPttK7L/DJXVJyru1 H0/CUDHus9g//Av89uCgz4vmpgbZPRgfrAtOJ/pKsunQUE248tAoMZg+T2UdZP8xjkmY Y/QdkDeHg6XeVFXpz1j4WPJByvUpbpXulo5SHQ/kJ8XdIgz8hHQX2coDs2pi4b66VBaR MwgFUh9gGgAQ6Km7gxy6MpTfAcJ/249RzI+vRNQKAHw7sYSVbUnygTsciYrYJJJkWfXq +ejeLYp9sYgFsoUiMw/XNWom/j5AjSLuhzHsAcZwn6UYG/0UgF7CBozyQcpeaWUKZw8K jqqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682612660; x=1685204660; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jj5QT1yI1Yn4DschSmlhYBQXITm427STmY5/fgnqXfU=; b=ZYtETxG2y6IQquvtDqa/7oaZLghyCFA/F/w2dj/YAuC1N+cNzGO3NcIIiO3JTYq5vy 9nyg+XNppfGRXPCLI84ADaGRrRuSIwebbDF+Ede1/z1WVDEhibQjTfSpo4fFEKySqmXw iaKMGOjSfPcIEA6chFTk1wMetz053fXuF+Vi/UcE6ah/bgpG5ZB5IKgpX/i4P9UQ4Q5d 0mDHsyXcVXYolxN+CzCNxnyF/8fjS5iNp07XUlWyxKr4JaYr6lXCslcAX/f4MG1ufJ7c UzeVxt+h/muzCKp9/rnQ5z0pnkaHwTEhK/rhVjtqWdsyyXjnfPt8SSU/N76IZAp8sfXK sXrg== X-Gm-Message-State: AC+VfDxvK8iQEwX/Yje6eLb1g0E2n4/JthsBgfk7OAgOZHVbMS4/SIt3 XlirGN2o/CDOxDAVXdIWljaoAX8fyPYSmKFAwbwzLYlj+tk= X-Received: by 2002:a17:903:ca:b0:1a8:1e36:b4b9 with SMTP id x10-20020a17090300ca00b001a81e36b4b9mr1807816plc.48.1682612659971; Thu, 27 Apr 2023 09:24:19 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id n19-20020a170902969300b001a6db2bef16sm11815906plp.303.2023.04.27.09.24.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 09:24:19 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v5 08/11] RISC-V: Weaken LR/SC pairs Date: Thu, 27 Apr 2023 09:22:58 -0700 Message-Id: <20230427162301.1151333-9-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230427162301.1151333-1-patrick@rivosinc.com> References: <20230414170942.1695672-1-patrick@rivosinc.com> <20230427162301.1151333-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764347563040902142?= X-GMAIL-MSGID: =?utf-8?q?1764347563040902142?= Introduce the %I and %J flags for setting the .aqrl bits on LR/SC pairs as needed. Atomic compare and exchange ops provide success and failure memory models. C++17 and later place no restrictions on the relative strength of each model, so ensure we cover both by using a model that enforces the ordering of both given models. This change brings LR/SC ops in line with table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_union_memmodels): Expose riscv_union_memmodels function to sync.md. * config/riscv/riscv.cc (riscv_union_memmodels): Add function to get the union of two memmodels in sync.md. (riscv_print_operand): Add %I and %J flags that output the optimal LR/SC flag bits for a given memory model. * config/riscv/sync.md: Remove static .aqrl bits on LR op/.rl bits on SC op and replace with optimized %I, %J flags. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Consolidate tests in [PATCH v3 10/10] --- v5 Changelog: * Also optimize subword LR/SC ops based on given memory model. --- gcc/config/riscv/riscv-protos.h | 3 + gcc/config/riscv/riscv.cc | 44 ++++++++++++ gcc/config/riscv/sync.md | 114 +++++++++++++++++++------------- 3 files changed, 114 insertions(+), 47 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index f87661bde2c..5fa9e1122ab 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -22,6 +22,8 @@ along with GCC; see the file COPYING3. If not see #ifndef GCC_RISCV_PROTOS_H #define GCC_RISCV_PROTOS_H +#include "memmodel.h" + /* Symbol types we understand. The order of this list must match that of the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */ enum riscv_symbol_type { @@ -81,6 +83,7 @@ extern bool riscv_v_ext_vector_mode_p (machine_mode); extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *); extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *); +extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); /* Routines implemented in riscv-c.cc. */ void riscv_cpu_cpp_builtins (cpp_reader *); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 9eba03ac189..69e9b2aa548 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4289,6 +4289,36 @@ riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc) fputc (')', file); } +/* Return the memory model that encapuslates both given models. */ + +enum memmodel +riscv_union_memmodels (enum memmodel model1, enum memmodel model2) +{ + model1 = memmodel_base (model1); + model2 = memmodel_base (model2); + + enum memmodel weaker = model1 <= model2 ? model1: model2; + enum memmodel stronger = model1 > model2 ? model1: model2; + + switch (stronger) + { + case MEMMODEL_SEQ_CST: + case MEMMODEL_ACQ_REL: + return stronger; + case MEMMODEL_RELEASE: + if (weaker == MEMMODEL_ACQUIRE || weaker == MEMMODEL_CONSUME) + return MEMMODEL_ACQ_REL; + else + return stronger; + case MEMMODEL_ACQUIRE: + case MEMMODEL_CONSUME: + case MEMMODEL_RELAXED: + return stronger; + default: + gcc_unreachable (); + } +} + /* Return true if the .AQ suffix should be added to an AMO to implement the acquire portion of memory model MODEL. */ @@ -4342,6 +4372,8 @@ riscv_memmodel_needs_amo_release (enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. + 'I' Print the LR suffix for memory model OP. + 'J' Print the SC suffix for memory model OP. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. @@ -4511,6 +4543,18 @@ riscv_print_operand (FILE *file, rtx op, int letter) fputs (".rl", file); break; + case 'I': + if (model == MEMMODEL_SEQ_CST) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire (model)) + fputs (".aq", file); + break; + + case 'J': + if (riscv_memmodel_needs_amo_release (model)) + fputs (".rl", file); + break; + case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 9a3b57bd09f..3e6345e83a3 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -116,21 +116,22 @@ (unspec_volatile:SI [(any_atomic:SI (match_dup 1) (match_operand:SI 2 "register_operand" "rI")) ;; value for op - (match_operand:SI 3 "register_operand" "rI")] ;; mask + (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_OLD_OP_SUBWORD)) - (match_operand:SI 4 "register_operand" "rI") ;; not_mask - (clobber (match_scratch:SI 5 "=&r")) ;; tmp_1 - (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_2 + (match_operand:SI 4 "register_operand" "rI") ;; mask + (match_operand:SI 5 "register_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 6 "=&r")) ;; tmp_1 + (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2 "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" - "lr.w.aqrl\t%0, %1\;" - "\t%5, %0, %2\;" - "and\t%5, %5, %3\;" - "and\t%6, %0, %4\;" - "or\t%6, %6, %5\;" - "sc.w.rl\t%5, %6, %1\;" - "bnez\t%5, 1b"; + "lr.w%I3\t%0, %1\;" + "\t%6, %0, %2\;" + "and\t%6, %6, %4\;" + "and\t%7, %0, %5\;" + "or\t%7, %7, %6\;" + "sc.w%J3\t%6, %7, %1\;" + "bnez\t%6, 1b"; } [(set (attr "length") (const_int 28))]) @@ -151,6 +152,7 @@ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; rtx value = operands[2]; + rtx model = operands[3]; rtx aligned_mem = gen_reg_rtx (SImode); rtx shift = gen_reg_rtx (SImode); rtx mask = gen_reg_rtx (SImode); @@ -162,7 +164,7 @@ riscv_lshift_subword (mode, value, shift, &shifted_value); emit_insn (gen_subword_atomic_fetch_strong_nand (old, aligned_mem, - shifted_value, + shifted_value, model, mask, not_mask)); emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, @@ -180,22 +182,23 @@ (unspec_volatile:SI [(not:SI (and:SI (match_dup 1) (match_operand:SI 2 "register_operand" "rI"))) ;; value for op - (match_operand:SI 3 "register_operand" "rI")] ;; mask + (match_operand:SI 3 "const_int_operand")] ;; mask UNSPEC_SYNC_OLD_OP_SUBWORD)) - (match_operand:SI 4 "register_operand" "rI") ;; not_mask - (clobber (match_scratch:SI 5 "=&r")) ;; tmp_1 - (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_2 + (match_operand:SI 4 "register_operand" "rI") ;; mask + (match_operand:SI 5 "register_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 6 "=&r")) ;; tmp_1 + (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_2 "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" - "lr.w.aqrl\t%0, %1\;" - "and\t%5, %0, %2\;" - "not\t%5, %5\;" - "and\t%5, %5, %3\;" - "and\t%6, %0, %4\;" - "or\t%6, %6, %5\;" - "sc.w.rl\t%5, %6, %1\;" - "bnez\t%5, 1b"; + "lr.w%I3\t%0, %1\;" + "and\t%6, %0, %2\;" + "not\t%6, %6\;" + "and\t%6, %6, %4\;" + "and\t%7, %0, %5\;" + "or\t%7, %7, %6\;" + "sc.w%J3\t%6, %7, %1\;" + "bnez\t%6, 1b"; } [(set (attr "length") (const_int 32))]) @@ -216,6 +219,7 @@ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; rtx value = operands[2]; + rtx model = operands[3]; rtx aligned_mem = gen_reg_rtx (SImode); rtx shift = gen_reg_rtx (SImode); rtx mask = gen_reg_rtx (SImode); @@ -228,7 +232,8 @@ emit_insn (gen_subword_atomic_fetch_strong_ (old, aligned_mem, shifted_value, - mask, not_mask)); + model, mask, + not_mask)); emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, gen_lowpart (QImode, shift))); @@ -261,6 +266,7 @@ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; rtx value = operands[2]; + rtx model = operands[3]; rtx aligned_mem = gen_reg_rtx (SImode); rtx shift = gen_reg_rtx (SImode); rtx mask = gen_reg_rtx (SImode); @@ -272,7 +278,8 @@ riscv_lshift_subword (mode, value, shift, &shifted_value); emit_insn (gen_subword_atomic_exchange_strong (old, aligned_mem, - shifted_value, not_mask)); + shifted_value, model, + not_mask)); emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, gen_lowpart (QImode, shift))); @@ -286,18 +293,19 @@ (match_operand:SI 1 "memory_operand" "+A")) ;; mem location (set (match_dup 1) (unspec_volatile:SI - [(match_operand:SI 2 "reg_or_0_operand" "rI") ;; value - (match_operand:SI 3 "reg_or_0_operand" "rI")] ;; not_mask + [(match_operand:SI 2 "reg_or_0_operand" "rI") ;; value + (match_operand:SI 3 "const_int_operand")] ;; model UNSPEC_SYNC_EXCHANGE_SUBWORD)) - (clobber (match_scratch:SI 4 "=&r"))] ;; tmp_1 + (match_operand:SI 4 "reg_or_0_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 5 "=&r"))] ;; tmp_1 "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" - "lr.w.aqrl\t%0, %1\;" - "and\t%4, %0, %3\;" - "or\t%4, %4, %2\;" - "sc.w.rl\t%4, %4, %1\;" - "bnez\t%4, 1b"; + "lr.w%I3\t%0, %1\;" + "and\t%5, %0, %4\;" + "or\t%5, %5, %2\;" + "sc.w%J3\t%5, %5, %1\;" + "bnez\t%5, 1b"; } [(set (attr "length") (const_int 20))]) @@ -313,10 +321,15 @@ (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" { + enum memmodel model_success = (enum memmodel) INTVAL (operands[4]); + enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]); + /* Find the union of the two memory models so we can satisfy both success + and failure memory models. */ + operands[5] = GEN_INT (riscv_union_memmodels (model_success, model_failure)); return "1:\;" - "lr..aqrl\t%0,%1\;" + "lr.%I5\t%0,%1\;" "bne\t%0,%z2,1f\;" - "sc..rl\t%6,%z3,%1\;" + "sc.%J5\t%6,%z3,%1\;" "bnez\t%6,1b\;" "1:"; } @@ -440,9 +453,15 @@ emit_move_insn (shifted_o, gen_rtx_AND (SImode, shifted_o, mask)); emit_move_insn (shifted_n, gen_rtx_AND (SImode, shifted_n, mask)); + enum memmodel model_success = (enum memmodel) INTVAL (operands[4]); + enum memmodel model_failure = (enum memmodel) INTVAL (operands[5]); + /* Find the union of the two memory models so we can satisfy both success + and failure memory models. */ + rtx model = GEN_INT (riscv_union_memmodels (model_success, model_failure)); + emit_insn (gen_subword_atomic_cas_strong (old, aligned_mem, shifted_o, shifted_n, - mask, not_mask)); + model, mask, not_mask)); emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, gen_lowpart (QImode, shift))); @@ -459,19 +478,20 @@ (unspec_volatile:SI [(match_operand:SI 2 "reg_or_0_operand" "rJ") ;; expected value (match_operand:SI 3 "reg_or_0_operand" "rJ")] ;; desired value UNSPEC_COMPARE_AND_SWAP_SUBWORD)) - (match_operand:SI 4 "register_operand" "rI") ;; mask - (match_operand:SI 5 "register_operand" "rI") ;; not_mask - (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_1 + (match_operand:SI 4 "const_int_operand") ;; model + (match_operand:SI 5 "register_operand" "rI") ;; mask + (match_operand:SI 6 "register_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 7 "=&r"))] ;; tmp_1 "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" - "lr.w.aqrl\t%0, %1\;" - "and\t%6, %0, %4\;" - "bne\t%6, %z2, 1f\;" - "and\t%6, %0, %5\;" - "or\t%6, %6, %3\;" - "sc.w.rl\t%6, %6, %1\;" - "bnez\t%6, 1b\;" + "lr.w%I4\t%0, %1\;" + "and\t%7, %0, %5\;" + "bne\t%7, %z2, 1f\;" + "and\t%7, %0, %6\;" + "or\t%7, %7, %3\;" + "sc.w%J4\t%7, %7, %1\;" + "bnez\t%7, 1b\;" "1:"; } [(set (attr "length") (const_int 28))])