From patchwork Thu Apr 27 16:23:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 88316 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp391130vqo; Thu, 27 Apr 2023 09:30:37 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7X2VJ9wUW6ildn5zW3s1SNxxuM2y0xdMWNwZ0PfEwk7EQ6iU3xargAYuSLht24czKOx+Uk X-Received: by 2002:a17:906:6c6:b0:94b:769f:3ba3 with SMTP id v6-20020a17090606c600b0094b769f3ba3mr6864795ejb.8.1682613037718; Thu, 27 Apr 2023 09:30:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682613037; cv=none; d=google.com; s=arc-20160816; b=Gti5SZVpa7u9UUAgbshYgJN4DCKraGrubklhnDVsMc8plT/3Pri+NHvQdq0oK1PRbE dQXUqJQVVWIZluKMRY9m9mXQoJ49X3WMyzBVFoUfdy24NKuoEO8nY2wmBOUGa9A0z6vd 40Dv9jSGN9iAob6VvPl7LdwNp8dy2U6iLoqQbOaMbUwlQAbXKo5rjoRXjsMs+vsm1xQB BrwG5TEMdzaELDvfBDZIiAM6FbsOb2RiV2TiCZSN/bG77y6pIlP2bNYhpPInH3yu/nET 0aFhSb81cyVqAW9tVT/tB3nS4/ZHE/0In5Pl86lrRvshMtJq+CjV3IvuLO78omC+V6Jn gfIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=IvyKDr2v4X4ElhLlgaJJpRQn05qma67Q3wHj7B2b4Fo=; b=x2cq9K7qaeNuyvJhy6HyJJlcNOL7A6jlrdsch1bW4qSMT/fl3CM1iadgBymuQf+Dfa HKpVJkDnKlTOtdXzBE9klZ9GMX5IPlRurrf8xomJxNN9VSbV4J/cVd5ZFq17P/AvV/wl FpnJM4yanVdieg//cZw2wCRqZm/sSsxFFyhJWC1OzUui0jVdjOjG2IYCK8zd3A2Cmj0Z EMGiDsUU/5yZ3bVWn7CTkYVUamLBYOuRTqb1f6uv4Dde/QAYevn0ueP0zLJDLvkcF+fo sunHO1DPJREI+ILYLFIU77t8bf6qTtoI6D9tTarfQBRYr0pNCyytRrtWCcQmnnpzVdtd qong== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=FFHSca6M; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id l3-20020aa7d943000000b0050494223599si15317140eds.296.2023.04.27.09.30.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 09:30:37 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=FFHSca6M; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8CE6B392AC01 for ; Thu, 27 Apr 2023 16:25:48 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x642.google.com (mail-pl1-x642.google.com [IPv6:2607:f8b0:4864:20::642]) by sourceware.org (Postfix) with ESMTPS id 84CAB3855586 for ; Thu, 27 Apr 2023 16:24:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 84CAB3855586 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x642.google.com with SMTP id d9443c01a7336-1a682eee3baso64870615ad.0 for ; Thu, 27 Apr 2023 09:24:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1682612665; x=1685204665; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IvyKDr2v4X4ElhLlgaJJpRQn05qma67Q3wHj7B2b4Fo=; b=FFHSca6MMDWzyPCfC9bPyqRxGldOKay9rlhS9hEh0UW0ry+h1e+IPgg8DrVA52sswk VFfsXOoMrrDaMJ1d2C0ZG415JrM3+z5Kv+VpJ4EjmsWRI9DhlJ89YJU7jNjmW+J7fHHm TkHTKk8PzGMqqcTF29dJQDFmF0UeGs7Y9OZ2aTLoCR+ohx4aGRPf63f7rzpZwyhMN+tS wMvKxmWmmtUFc4UY3UBiajfHYMZrzpk8QTp2VcuVuyehlFbdn9LtwxS8C+Kkmcs6gDFq ZgGuhUNJERAHqauH/GxReyvLqYUdmyyz7qKI9oroH5PqNX45Brag/rPtaotEfWWfy8dk rPiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682612665; x=1685204665; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IvyKDr2v4X4ElhLlgaJJpRQn05qma67Q3wHj7B2b4Fo=; b=ifq1TP7x9uRDS5SIfPIdP/mWs2UJ8VjciIcihnKoRuESJ25s/G2dAjn/m8Nec7R/U7 J742spuLXiQZMtd0Q7PXWgH7aXD5opndAMtE44DPqaBcL0EMlbcBoGXppGUzRh5Vp4HE J11mgK9ONIUGiJC7cLVJUevktnR5+4iby41WbWEuDSNYmO3Ld7eNS9E4ZjEwEDJV7s2/ fk2y7TNsqFAd/bQNl4Ti7rlG7LxFLqk0KPaGDEhVQk7SdjitDTqJKDzyMjBa9wDDbOWp rT52U47E2JmJl379P+scyxaj2f1R0YM2b9LkmdwTXKeeSBBrECw5VWgCcq9Vqc3BI1Xm jjzw== X-Gm-Message-State: AC+VfDwFSDQVdFhb2LMqyHmdtGZpA5mra9Bf4klJH+panAAH+dYVIno4 AhYE2eu4GMCHNWhdnRb/Jrz+IV0CEvHgzhwOJrmK3IeC0dc= X-Received: by 2002:a17:902:d505:b0:1a9:9c5d:9fac with SMTP id b5-20020a170902d50500b001a99c5d9facmr2703609plg.33.1682612664769; Thu, 27 Apr 2023 09:24:24 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id n19-20020a170902969300b001a6db2bef16sm11815906plp.303.2023.04.27.09.24.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Apr 2023 09:24:24 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v5 11/11] RISC-V: Table A.6 conformance tests Date: Thu, 27 Apr 2023 09:23:01 -0700 Message-Id: <20230427162301.1151333-12-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230427162301.1151333-1-patrick@rivosinc.com> References: <20230414170942.1695672-1-patrick@rivosinc.com> <20230427162301.1151333-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764347648772061764?= X-GMAIL-MSGID: =?utf-8?q?1764347648772061764?= These tests cover basic cases to ensure the atomic mappings follow the strengthened Table A.6 mappings that are compatible with Table A.7. 2023-04-27 Patrick O'Neill gcc/testsuite/ChangeLog: * gcc.target/riscv/amo-table-a-6-amo-add-1.c: New test. * gcc.target/riscv/amo-table-a-6-amo-add-2.c: New test. * gcc.target/riscv/amo-table-a-6-amo-add-3.c: New test. * gcc.target/riscv/amo-table-a-6-amo-add-4.c: New test. * gcc.target/riscv/amo-table-a-6-amo-add-5.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-1.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-2.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-3.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-4.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-5.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-6.c: New test. * gcc.target/riscv/amo-table-a-6-compare-exchange-7.c: New test. * gcc.target/riscv/amo-table-a-6-fence-1.c: New test. * gcc.target/riscv/amo-table-a-6-fence-2.c: New test. * gcc.target/riscv/amo-table-a-6-fence-3.c: New test. * gcc.target/riscv/amo-table-a-6-fence-4.c: New test. * gcc.target/riscv/amo-table-a-6-fence-5.c: New test. * gcc.target/riscv/amo-table-a-6-load-1.c: New test. * gcc.target/riscv/amo-table-a-6-load-2.c: New test. * gcc.target/riscv/amo-table-a-6-load-3.c: New test. * gcc.target/riscv/amo-table-a-6-store-1.c: New test. * gcc.target/riscv/amo-table-a-6-store-2.c: New test. * gcc.target/riscv/amo-table-a-6-store-compat-3.c: New test. * gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c: New test. * gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c: New test. * gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c: New test. * gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c: New test. * gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c: New test. Signed-off-by: Patrick O'Neill --- .../gcc.target/riscv/amo-table-a-6-amo-add-1.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-2.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-3.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-4.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-amo-add-5.c | 8 ++++++++ .../riscv/amo-table-a-6-compare-exchange-1.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-2.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-3.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-4.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-5.c | 10 ++++++++++ .../riscv/amo-table-a-6-compare-exchange-6.c | 11 +++++++++++ .../riscv/amo-table-a-6-compare-exchange-7.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-1.c | 8 ++++++++ .../gcc.target/riscv/amo-table-a-6-fence-2.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-3.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-4.c | 10 ++++++++++ .../gcc.target/riscv/amo-table-a-6-fence-5.c | 10 ++++++++++ gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c | 9 +++++++++ gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c | 11 +++++++++++ .../gcc.target/riscv/amo-table-a-6-store-1.c | 9 +++++++++ .../gcc.target/riscv/amo-table-a-6-store-2.c | 11 +++++++++++ .../gcc.target/riscv/amo-table-a-6-store-compat-3.c | 11 +++++++++++ .../riscv/amo-table-a-6-subword-amo-add-1.c | 9 +++++++++ .../riscv/amo-table-a-6-subword-amo-add-2.c | 9 +++++++++ .../riscv/amo-table-a-6-subword-amo-add-3.c | 9 +++++++++ .../riscv/amo-table-a-6-subword-amo-add-4.c | 9 +++++++++ .../riscv/amo-table-a-6-subword-amo-add-5.c | 9 +++++++++ 28 files changed, 266 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c new file mode 100644 index 00000000000..cb044f78fcf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c new file mode 100644 index 00000000000..c8445321989 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.aq\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c new file mode 100644 index 00000000000..dfec3020c91 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-3.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.rl\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c new file mode 100644 index 00000000000..b9f90e199b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-4.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.aqrl\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c new file mode 100644 index 00000000000..94c4bec933b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-amo-add-5.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler "amoadd.w.aqrl\t" } } */ + +void +foo (int* bar, int* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c new file mode 100644 index 00000000000..a9141cde48f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c new file mode 100644 index 00000000000..b1ebb20e2f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_CONSUME, __ATOMIC_CONSUME); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c new file mode 100644 index 00000000000..47d8d02f7e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c new file mode 100644 index 00000000000..af6e1d69c75 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c new file mode 100644 index 00000000000..ceb5660b6af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-5.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c new file mode 100644 index 00000000000..7b012fb1288 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-6.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* Mixed mappings need to be unioned. */ +/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_RELEASE, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c new file mode 100644 index 00000000000..5adec6f7a19 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-compare-exchange-7.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that compare exchange mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (int bar, int baz, int qux) +{ + __atomic_compare_exchange_n(&bar, &baz, qux, 1, __ATOMIC_SEQ_CST, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c new file mode 100644 index 00000000000..b8c28013ef3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-not "fence\t" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c new file mode 100644 index 00000000000..117f9036e39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c new file mode 100644 index 00000000000..4b6dd7a9aa7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c new file mode 100644 index 00000000000..d40d3bc37db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence.tso" 1 } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c new file mode 100644 index 00000000000..71f76c27789 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-fence-5.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* Verify that fence mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ + +int main() { + __atomic_thread_fence(__ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c new file mode 100644 index 00000000000..8278198072e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that load mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-not "fence\t" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_load(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c new file mode 100644 index 00000000000..84b6cc542ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that load mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_load(bar, baz, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c new file mode 100644 index 00000000000..3f15041d117 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-load-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that load mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\tr,rw" 1 } } */ +/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence\trw,w" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_load(bar, baz, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c new file mode 100644 index 00000000000..c200bd1d11d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that store mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-not "fence\t" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_store(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c new file mode 100644 index 00000000000..1cf366b5986 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that store mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence\trw,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_store(bar, baz, __ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c new file mode 100644 index 00000000000..288e1493156 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-store-compat-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* Verify that store mapping are compatible with Table A.6 & A.7. */ +/* { dg-final { scan-assembler-times "fence\trw,w" 1 } } */ +/* { dg-final { scan-assembler-times "fence\trw,rw" 1 } } */ +/* { dg-final { scan-assembler-not "fence\tr,rw" } } */ +/* { dg-final { scan-assembler-not "fence.tso" } } */ + +void +foo (int* bar, int* baz) { + __atomic_store(bar, baz, __ATOMIC_SEQ_CST); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c new file mode 100644 index 00000000000..9efa25ddf26 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +void +foo (short* bar, short* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_RELAXED); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c new file mode 100644 index 00000000000..536f7e9228f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w\t" 1 } } */ + +void +foo (short* bar, short* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQUIRE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c new file mode 100644 index 00000000000..69c2324a1f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (short* bar, short* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_RELEASE); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c new file mode 100644 index 00000000000..a0779b4c421 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-4.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (short* bar, short* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_ACQ_REL); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c new file mode 100644 index 00000000000..f88901dc717 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo-table-a-6-subword-amo-add-5.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* Verify that subword atomic op mappings match Table A.6's recommended mapping. */ +/* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */ +/* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */ + +void +foo (short* bar, short* baz) { + __atomic_add_fetch(bar, baz, __ATOMIC_SEQ_CST); +}