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Thu, 27 Apr 2023 09:24:22 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v5 10/11] RISC-V: Weaken atomic loads Date: Thu, 27 Apr 2023 09:23:00 -0700 Message-Id: <20230427162301.1151333-11-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230427162301.1151333-1-patrick@rivosinc.com> References: <20230414170942.1695672-1-patrick@rivosinc.com> <20230427162301.1151333-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764347509245940482?= X-GMAIL-MSGID: =?utf-8?q?1764347509245940482?= This change brings atomic loads in line with table A.6 of the ISA manual. 2023-04-27 Patrick O'Neill gcc/ChangeLog: * config/riscv/sync.md (atomic_load): Implement atomic load mapping. Signed-off-by: Patrick O'Neill --- gcc/config/riscv/sync.md | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index ba132d8a1ce..6e7c762ac57 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -26,6 +26,7 @@ UNSPEC_SYNC_OLD_OP_SUBWORD UNSPEC_SYNC_EXCHANGE UNSPEC_SYNC_EXCHANGE_SUBWORD + UNSPEC_ATOMIC_LOAD UNSPEC_ATOMIC_STORE UNSPEC_MEMORY_BARRIER ]) @@ -66,8 +67,31 @@ ;; Atomic memory operations. -;; Implement atomic stores with conservative fences. Fall back to fences for -;; atomic loads. +(define_insn "atomic_load" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec_volatile:GPR + [(match_operand:GPR 1 "memory_operand" "A") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPEC_ATOMIC_LOAD))] + "TARGET_ATOMIC" + { + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + model = memmodel_base (model); + + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw\;" + "l\t%0,%1\;" + "fence\tr,rw"; + if (model == MEMMODEL_ACQUIRE) + return "l\t%0,%1\;" + "fence\tr,rw"; + else + return "l\t%0,%1"; + } + [(set_attr "type" "atomic") + (set (attr "length") (const_int 12))]) + +;; Implement atomic stores with conservative fences. ;; This allows us to be compatible with the ISA manual Table A.6 and Table A.7. (define_insn "atomic_store" [(set (match_operand:GPR 0 "memory_operand" "=A")