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(riscv_vector_mask_mode_p): Ditto. (riscv_vector_get_mask_mode): Ditto. (emit_vlmax_vsetvl): Ditto. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto. (vlmul_field_enum): Ditto. * config/riscv/riscv-v.cc (emit_vlmax_vsetvl): Remove static scope. * config/riscv/predicates.md (p_reg_or_const_csr_operand): New predicate. (vector_reg_or_const_dup_operand): Ditto. * config/riscv/riscv-opts.h (riscv_vector_bits_enum): New enum. (riscv_vector_lmul_enum): Ditto. (vlmul_field_enum): Ditto. --- gcc/config/riscv/predicates.md | 13 +++++++++++++ gcc/config/riscv/riscv-opts.h | 29 +++++++++++++++++++++++++++++ gcc/config/riscv/riscv-protos.h | 9 +++++++++ 3 files changed, 51 insertions(+) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 8654dbc5943..b3f2d622c7b 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -264,6 +264,14 @@ }) ;; Predicates for the V extension. +(define_special_predicate "p_reg_or_const_csr_operand" + (match_code "reg, subreg, const_int") +{ + if (CONST_INT_P (op)) + return satisfies_constraint_K (op); + return GET_MODE (op) == Pmode; +}) + (define_special_predicate "vector_length_operand" (ior (match_operand 0 "pmode_register_operand") (match_operand 0 "const_csr_operand"))) @@ -291,6 +299,11 @@ (and (match_code "const_vector") (match_test "rtx_equal_p (op, riscv_vector::gen_scalar_move_mask (GET_MODE (op)))"))) +(define_predicate "vector_reg_or_const_dup_operand" + (ior (match_operand 0 "register_operand") + (match_test "const_vec_duplicate_p (op) + && !CONST_POLY_INT_P (CONST_VECTOR_ELT (op, 0))"))) + (define_predicate "vector_mask_operand" (ior (match_operand 0 "register_operand") (match_operand 0 "vector_all_trues_mask_operand"))) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index cf0cd669be4..af77df11430 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -67,6 +67,35 @@ enum stack_protector_guard { SSP_GLOBAL /* global canary */ }; +/* RISC-V auto-vectorization preference. */ +enum riscv_autovec_preference_enum { + NO_AUTOVEC, + RVV_SCALABLE, + RVV_FIXED_VLMAX +}; + +/* vectorization factor. */ +enum riscv_vector_lmul_enum +{ + RVV_LMUL1 = 1, + RVV_LMUL2 = 2, + RVV_LMUL4 = 4, + RVV_LMUL8 = 8 +}; + +enum vlmul_field_enum +{ + VLMUL_FIELD_000, /* LMUL = 1. */ + VLMUL_FIELD_001, /* LMUL = 2. */ + VLMUL_FIELD_010, /* LMUL = 4. */ + VLMUL_FIELD_011, /* LMUL = 8. */ + VLMUL_FIELD_100, /* RESERVED. */ + VLMUL_FIELD_101, /* LMUL = 1/8. */ + VLMUL_FIELD_110, /* LMUL = 1/4. */ + VLMUL_FIELD_111, /* LMUL = 1/2. */ + MAX_VLMUL_FIELD +}; + #define MASK_ZICSR (1 << 0) #define MASK_ZIFENCEI (1 << 1) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 5244e8dcbf0..55056222e57 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -237,4 +237,13 @@ extern const char* th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE); #endif +/* Routines implemented in riscv-v.cc. */ + +namespace riscv_vector { +extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode); +extern bool riscv_vector_mask_mode_p (machine_mode); +extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode); +extern rtx get_mask_policy_no_pred (); +extern rtx get_tail_policy_no_pred (); +} #endif /* ! GCC_RISCV_PROTOS_H */