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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id n13-20020aa7db4d000000b00504a27c35cbsi14309801edt.313.2023.04.26.13.54.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Apr 2023 13:54:28 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=qVAzKR+W; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EB57C3858436 for ; Wed, 26 Apr 2023 20:54:23 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) by sourceware.org (Postfix) with ESMTPS id A17673858C54 for ; Wed, 26 Apr 2023 20:53:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A17673858C54 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pg1-x542.google.com with SMTP id 41be03b00d2f7-5286311be47so2492087a12.1 for ; Wed, 26 Apr 2023 13:53:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1682542435; x=1685134435; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=rIYWDp3fS42QoOVSL4ycIZbWyzEajXcb7mhumLc8wa0=; b=qVAzKR+W32KPRW05QdMxkk83gGHk+H95vRRIVovFRKGvoc6bBhZEhbDg6ESFDkxMac Fq479FQO86E6fN+xhim1KTnKIJjh25uD5jD5YZDD/TpjuNNbyzTzQfZYe6aL+g2F5eSp TkKe6LsVUYj/pNvT77GrdKuHHPz8UR62HHt+XP99dIpgKY25tWdeCe63hv3+BBPoUgQT kodkdtYn1ClvDsF2vSnSP96PCJ/FuUvbwyNDXmYbeXqD/zRmhr2QVpGoafrffmuYQQkU YwbkOKlbbvDR1x2uwB4P5KHlUZtacWim0FjQsP91evqIo8038zFsu0eG2KlacucPREFh eI4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682542435; x=1685134435; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=rIYWDp3fS42QoOVSL4ycIZbWyzEajXcb7mhumLc8wa0=; b=Ak+IW7pOpapfV+YlC+DfBkmbqdQHkn8+RoyNzIwb8uHjKGSo1x15g+SLaTSY9UqMoS Gh9FddUTvaiW68ql9wlFE5dJnbyKd9i5+lxW95jnaHIZNWk9XIjqzNd5vlSrYp0o8eAd 6JU6mpexPckzf72Vvcm5oC54tbL9KS+pCW+U0N49WmUVuvRPfGFgtNlVc6gVBJNghPRN 4wXxzqhV5Rsiiopz5Gf9BFEuH6I9Ws7gHFhimFek0YGhYS9WLj7NkVlQ1FRSWZP4sVVh TrUSeKWkYjvuSOvy5ScyB4CzqHiZg8kqwA7XPgQIh3RNl3abWeeD/56aj+Cz8mIV42mG /ztw== X-Gm-Message-State: AAQBX9cLxhjk80tqXdIrYxJJ3YXwrigrx0N9Q3Uaz21V60zMZDEdJpAc Zjx+2SSNKmipBh8xz01A+5c53ST/JKM8AWwcJ6btoK833T0= X-Received: by 2002:a17:90a:b904:b0:247:4c7:4d53 with SMTP id p4-20020a17090ab90400b0024704c74d53mr21873471pjr.36.1682542435190; Wed, 26 Apr 2023 13:53:55 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id a11-20020a634d0b000000b004e28be19d1csm9935325pgb.32.2023.04.26.13.53.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Apr 2023 13:53:54 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: rep.dot.nop@gmail.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH] RISC-V: Fix sync.md and riscv.cc whitespace errors Date: Wed, 26 Apr 2023 13:53:49 -0700 Message-Id: <20230426205349.1131469-1-patrick@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, MEDICAL_SUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764273651267499555?= X-GMAIL-MSGID: =?utf-8?q?1764273651267499555?= This patch fixes whitespace errors introduced with https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616807.html 2023-04-26 Patrick O'Neill gcc/ChangeLog: * config/riscv/riscv.cc: Fix whitespace. * config/riscv/sync.md: Fix whitespace. Signed-off-by: Patrick O'Neill --- Patch was checked with contrib/check_GNU_style.py Whitespace changes in this patch are 3 flavors: * Add space between function name and () * Remove space before square bracket[] * 2 spaces between end of comment and */ --- gcc/config/riscv/riscv.cc | 6 +++--- gcc/config/riscv/sync.md | 40 +++++++++++++++++++-------------------- 2 files changed, 23 insertions(+), 23 deletions(-) -- 2.34.1 diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 0f890469d7a..1529855a2b4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7193,7 +7193,7 @@ riscv_subword_address (rtx mem, rtx *aligned_mem, rtx *shift, rtx *mask, emit_move_insn (*mask, gen_rtx_ASHIFT (SImode, *mask, gen_lowpart (QImode, *shift))); - emit_move_insn (*not_mask, gen_rtx_NOT(SImode, *mask)); + emit_move_insn (*not_mask, gen_rtx_NOT (SImode, *mask)); } /* Leftshift a subword within an SImode register. */ @@ -7206,8 +7206,8 @@ riscv_lshift_subword (machine_mode mode, rtx value, rtx shift, emit_move_insn (value_reg, simplify_gen_subreg (SImode, value, mode, 0)); - emit_move_insn(*shifted_value, gen_rtx_ASHIFT (SImode, value_reg, - gen_lowpart (QImode, shift))); + emit_move_insn (*shifted_value, gen_rtx_ASHIFT (SImode, value_reg, + gen_lowpart (QImode, shift))); } /* Initialize the GCC target structure. */ diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 83be6431cb6..8e95ce77916 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -49,7 +49,7 @@ ;; conservatively emit a full FENCE. (define_insn "mem_thread_fence_1" [(set (match_operand:BLK 0 "" "") - (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) + (unspec:BLK[(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (match_operand:SI 1 "const_int_operand" "")] ;; model "" "fence\tiorw,iorw") @@ -128,10 +128,10 @@ { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_fetch_strong_nand to implement a LR/SC version of the - operation. */ + operation. */ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining - is disabled */ + is disabled. */ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; @@ -193,10 +193,10 @@ { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_fetch_strong_ to implement a LR/SC version of the - operation. */ + operation. */ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining - is disabled */ + is disabled. */ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; @@ -290,10 +290,10 @@ [(set (match_operand:GPR 0 "register_operand" "=&r") (match_operand:GPR 1 "memory_operand" "+A")) (set (match_dup 1) - (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "rJ") - (match_operand:GPR 3 "reg_or_0_operand" "rJ") - (match_operand:SI 4 "const_int_operand") ;; mod_s - (match_operand:SI 5 "const_int_operand")] ;; mod_f + (unspec_volatile:GPR[(match_operand:GPR 2 "reg_or_0_operand" "rJ") + (match_operand:GPR 3 "reg_or_0_operand" "rJ") + (match_operand:SI 4 "const_int_operand") ;; mod_s + (match_operand:SI 5 "const_int_operand")] ;; mod_f UNSPEC_COMPARE_AND_SWAP)) (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" @@ -367,7 +367,7 @@ { rtx difference = gen_rtx_MINUS (SImode, val, exp); compare = gen_reg_rtx (SImode); - emit_move_insn (compare, difference); + emit_move_insn (compare, difference); } if (word_mode != SImode) @@ -393,10 +393,10 @@ { /* We have no QImode/HImode atomics, so form a mask, then use subword_atomic_cas_strong to implement a LR/SC version of the - operation. */ + operation. */ /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining - is disabled */ + is disabled. */ rtx old = gen_reg_rtx (SImode); rtx mem = operands[1]; @@ -431,15 +431,15 @@ }) (define_insn "subword_atomic_cas_strong" - [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem - (match_operand:SI 1 "memory_operand" "+A")) ;; mem location + [(set (match_operand:SI 0 "register_operand" "=&r") ;; old value at mem + (match_operand:SI 1 "memory_operand" "+A")) ;; mem location (set (match_dup 1) - (unspec_volatile:SI [(match_operand:SI 2 "reg_or_0_operand" "rJ") ;; expected value - (match_operand:SI 3 "reg_or_0_operand" "rJ")] ;; desired value + (unspec_volatile:SI[(match_operand:SI 2 "reg_or_0_operand" "rJ") ;; expected value + (match_operand:SI 3 "reg_or_0_operand" "rJ")] ;; desired value UNSPEC_COMPARE_AND_SWAP_SUBWORD)) - (match_operand:SI 4 "register_operand" "rI") ;; mask - (match_operand:SI 5 "register_operand" "rI") ;; not_mask - (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_1 + (match_operand:SI 4 "register_operand" "rI") ;; mask + (match_operand:SI 5 "register_operand" "rI") ;; not_mask + (clobber (match_scratch:SI 6 "=&r"))] ;; tmp_1 "TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC" { return "1:\;" @@ -461,7 +461,7 @@ "TARGET_ATOMIC" { /* We have no QImode atomics, so use the address LSBs to form a mask, - then use an aligned SImode atomic. */ + then use an aligned SImode atomic. */ rtx result = operands[0]; rtx mem = operands[1]; rtx model = operands[2];