diff mbox series

RISC-V: ICE for vlmul_ext_v intrinsic API

Message ID 20230426120503.3207041-1-yanzhang.wang@intel.com
State Accepted
Headers
Series RISC-V: ICE for vlmul_ext_v intrinsic API |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Li, Pan2 via Gcc-patches April 26, 2023, 12:05 p.m. UTC 
  From: Yanzhang Wang <yanzhang.wang@intel.com>

	PR 109617

gcc/ChangeLog:

	* config/riscv/vector-iterators.md:

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/vector-iterators.md               |  3 ++-
 .../gcc.target/riscv/rvv/base/vlmul_ext-1.c        | 14 ++++++++++++++
 2 files changed, 16 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c

Comments

Li, Pan2 via Gcc-patches April 26, 2023, 12:22 p.m. UTC | #1 
Great! Thanks yanzhang.

Could you please help to add some text about the changes below? Or kito may meet some error by git hook when commit the PATCH.


gcc/ChangeLog:



                * config/riscv/vector-iterators.md:   <- add text for change.



gcc/testsuite/ChangeLog:



                * gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.

Pan

From: juzhe.zhong <juzhe.zhong@rivai.ai>
Sent: Wednesday, April 26, 2023 8:15 PM
To: Wang, Yanzhang <yanzhang.wang@intel.com>
Cc: gcc-patches@gcc.gnu.org; kito.cheng@sifive.com; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH] RISC-V: ICE for vlmul_ext_v intrinsic API

LGTM. Thanks for fixing my silly mistake.
---- Replied Message ----
From
yanzhang.wang@intel.com<yanzhang.wang@intel.com><mailto:yanzhang.wang@intel.com>
Date
04/26/2023 20:05
To
gcc-patches@gcc.gnu.org<gcc-patches@gcc.gnu.org><mailto:gcc-patches@gcc.gnu.org>
Cc
juzhe.zhong@rivai.ai<juzhe.zhong@rivai.ai><mailto:juzhe.zhong@rivai.ai>,
kito.cheng@sifive.com<kito.cheng@sifive.com><mailto:kito.cheng@sifive.com>,
pan2.li@intel.com<pan2.li@intel.com><mailto:pan2.li@intel.com>,
yanzhang.wang@intel.com<yanzhang.wang@intel.com><mailto:yanzhang.wang@intel.com>
Subject
[PATCH] RISC-V: ICE for vlmul_ext_v intrinsic API
diff mbox series

Patch

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index a8e856161d3..033659930d1 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -189,6 +189,7 @@ 
   (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128")
   (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128")
   (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
+  (VNx4DI "TARGET_VECTOR_ELEN_64")
   (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
   (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
   (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
@@ -220,7 +221,7 @@ 
 
 (define_mode_iterator VLMULEXT32 [
   (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN >= 128")
-  (VNx1HI "TARGET_MIN_VLEN < 128")
+  (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN >= 128")
 ])
 
 (define_mode_iterator VLMULEXT64 [
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
new file mode 100644
index 00000000000..501d98c5897
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include <riscv_vector.h>
+
+vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) {
+  return __riscv_vlmul_ext_v_i16mf4_i16m8(op1);
+}
+
+vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) {
+  return __riscv_vlmul_ext_v_i64m2_i64m8(op1);
+}
+
+/* { dg-final { scan-assembler-times {vs8r.v\s+[,\sa-x0-9()]+} 2} } */