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RISC-V: Add function comment for cleanup_insns.

Message ID 20230423113354.141950-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Add function comment for cleanup_insns. |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai April 23, 2023, 11:33 a.m. UTC 
  From: Juzhe-Zhong <juzhe.zhong@rivai.ai>

Address Jeff's comment: https://patchwork.sourceware.org/project/gcc/patch/20230330012804.110539-1-juzhe.zhong@rivai.ai/
Add a function comment.

gcc/ChangeLog:

        * config/riscv/riscv-vsetvl.cc (pass_vsetvl::pre_vsetvl): Add function comment for cleanup_insns.

---
 gcc/config/riscv/riscv-vsetvl.cc | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Comments

Kito Cheng April 24, 2023, 6:25 a.m. UTC | #1 
Pushed

On Sun, Apr 23, 2023 at 7:34 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> Address Jeff's comment: https://patchwork.sourceware.org/project/gcc/patch/20230330012804.110539-1-juzhe.zhong@rivai.ai/
> Add a function comment.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-vsetvl.cc (pass_vsetvl::pre_vsetvl): Add function comment for cleanup_insns.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
> index ac99028df43..fa68b8a0462 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -3998,6 +3998,21 @@ pass_vsetvl::pre_vsetvl (void)
>      commit_edge_insertions ();
>  }
>
> +/* Before VSETVL PASS, RVV instructions pattern is depending on AVL operand
> +   implicitly. Since we will emit VSETVL instruction and make RVV instructions
> +   depending on VL/VTYPE global status registers, we remove the such AVL operand
> +   in the RVV instructions pattern here in order to remove AVL dependencies when
> +   AVL operand is a register operand.
> +
> +   Before the VSETVL PASS:
> +     li a5,32
> +     ...
> +     vadd.vv (..., a5)
> +   After the VSETVL PASS:
> +     li a5,32
> +     vsetvli zero, a5, ...
> +     ...
> +     vadd.vv (..., const_int 0).  */
>  void
>  pass_vsetvl::cleanup_insns (void) const
>  {
> --
> 2.36.1
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index ac99028df43..fa68b8a0462 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -3998,6 +3998,21 @@  pass_vsetvl::pre_vsetvl (void)
     commit_edge_insertions ();
 }
 
+/* Before VSETVL PASS, RVV instructions pattern is depending on AVL operand
+   implicitly. Since we will emit VSETVL instruction and make RVV instructions
+   depending on VL/VTYPE global status registers, we remove the such AVL operand
+   in the RVV instructions pattern here in order to remove AVL dependencies when
+   AVL operand is a register operand.
+
+   Before the VSETVL PASS:
+     li a5,32
+     ...
+     vadd.vv (..., a5)
+   After the VSETVL PASS:
+     li a5,32
+     vsetvli zero, a5, ...
+     ...
+     vadd.vv (..., const_int 0).  */
 void
 pass_vsetvl::cleanup_insns (void) const
 {