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[8.43.85.97]) by mx.google.com with ESMTPS id l21-20020a170907915500b0094f10dbffb4si9683178ejs.551.2023.04.19.09.45.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Apr 2023 09:45:35 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3DA34382D824 for ; Wed, 19 Apr 2023 16:43:07 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by sourceware.org (Postfix) with ESMTPS id 66CB3385356C for ; Wed, 19 Apr 2023 16:42:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 66CB3385356C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp89t1681922544t7m4hdyi Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 20 Apr 2023 00:42:23 +0800 (CST) X-QQ-SSF: 01400000000000F0P000000A0000000 X-QQ-FEAT: DA0VEWY2eXph0eFaKNKJCsmbrbwI3i5L2+eD/G69ewWOwMQMR3Hn+WtwCluiK XR1JPqkJIEsqJj3I9hCDcT9L3rXiRWlBk6JWMtW2HY1tiBPGrLDg+Qzbic7gznFeqEP9bY5 yGyjpXAxQe+NRDpTs+WQbLljYS8z5s9ZjYYsRCIe9XaI/ZtOsJVB5ir+o9SPFneF56cUkjH gAqOdnQjx3dmSUC4HKQdfzIrsKqtUqTmal4uL3uyeM8T0KVT9NnhZF1ARGdFaYY7BeDI7Ai B9mZunhyixozmPQX1JY9R+d5G4t1Qp6XuWjnMuGJzoaiSZmsuSMgrImagAir5DsHs6q8eJx eUBZwaoZz3b/aI3YVgn04HrL5o/2qb/hMaa3ahTJZwVlYRuuojPnEBD1g5FVQ== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 13914274286111681805 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, Ju-Zhe Zhong Subject: [PATCH 2/3 V2] RISC-V: Enable basic auto-vectorization for RVV Date: Thu, 20 Apr 2023 00:42:13 +0800 Message-Id: <20230419164214.1032017-3-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 In-Reply-To: <20230419164214.1032017-1-juzhe.zhong@rivai.ai> References: <20230419164214.1032017-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763623813842554225?= X-GMAIL-MSGID: =?utf-8?q?1763623813842554225?= From: Ju-Zhe Zhong This patch enables auto-vectorization accurately according to '-march' And add len_load/len_store pattern. For example, for -march=rv32gc_zve32x, we should allow SEW = 64 RVV auto-vectorization. gcc/ChangeLog: * config/riscv/riscv-protos.h (preferred_simd_mode): Enable basic auto-vectorization support. * config/riscv/riscv-v.cc (autovec_use_vlmax_p): New function. (preferred_simd_mode): Ditto. * config/riscv/riscv.cc (riscv_convert_vector_bits): Enable basic auto-vectorization support. (riscv_preferred_simd_mode): New function. (TARGET_VECTORIZE_PREFERRED_SIMD_MODE): New target hook. * config/riscv/vector.md: include autovec.md * config/riscv/autovec.md: New file. --- gcc/config/riscv/autovec.md | 49 ++++++++++++++++++++++++++++++ gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 53 +++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv.cc | 24 ++++++++++++++- gcc/config/riscv/vector.md | 4 ++- 5 files changed, 129 insertions(+), 2 deletions(-) create mode 100644 gcc/config/riscv/autovec.md diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md new file mode 100644 index 00000000000..b5d46ff57ab --- /dev/null +++ b/gcc/config/riscv/autovec.md @@ -0,0 +1,49 @@ +;; Machine description for auto-vectorization using RVV for GNU compiler. +;; Copyright (C) 2023 Free Software Foundation, Inc. +;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; ========================================================================= +;; == Loads/Stores +;; ========================================================================= + +;; len_load/len_store is a sub-optimal pattern for RVV auto-vectorization support. +;; We will replace them when len_maskload/len_maskstore is supported in loop vectorizer. +(define_expand "len_load_" + [(match_operand:V 0 "register_operand") + (match_operand:V 1 "memory_operand") + (match_operand 2 "vector_length_operand") + (match_operand 3 "const_0_operand")] + "TARGET_VECTOR" +{ + riscv_vector::emit_nonvlmax_op (code_for_pred_mov (mode), operands[0], + operands[1], operands[2], mode); + DONE; +}) + +(define_expand "len_store_" + [(match_operand:V 0 "memory_operand") + (match_operand:V 1 "register_operand") + (match_operand 2 "vector_length_operand") + (match_operand 3 "const_0_operand")] + "TARGET_VECTOR" +{ + riscv_vector::emit_nonvlmax_op (code_for_pred_mov (mode), operands[0], + operands[1], operands[2], mode); + DONE; +}) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 5244e8dcbf0..2de9d40be46 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -207,6 +207,7 @@ enum vlen_enum bool slide1_sew64_helper (int, machine_mode, machine_mode, machine_mode, rtx *); rtx gen_avl_for_scalar_move (rtx); +machine_mode preferred_simd_mode (scalar_mode); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 99c414cc910..5e69427ac54 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -43,6 +43,7 @@ #include "optabs.h" #include "tm-constrs.h" #include "rtx-vector-builder.h" +#include "targhooks.h" using namespace riscv_vector; @@ -742,4 +743,56 @@ gen_avl_for_scalar_move (rtx avl) } } +/* SCALABLE means that the vector-length is agnostic (run-time invariant and + compile-time unknown). FIXED meands that the vector-length is specific + (compile-time known). Both RVV_SCALABLE and RVV_FIXED_VLMAX are doing + auto-vectorization using VLMAX vsetvl configuration. */ +static bool +autovec_use_vlmax_p (void) +{ + return riscv_autovec_preference == RVV_SCALABLE + || riscv_autovec_preference == RVV_FIXED_VLMAX; +} + +/* Return the vectorization machine mode for RVV according to LMUL. */ +machine_mode +preferred_simd_mode (scalar_mode mode) +{ + /* We only enable auto-vectorization when TARGET_MIN_VLEN >= 128 + which is -march=rv64gcv. Since GCC loop vectorizer report ICE + when we enable -march=rv64gc_zve32* and -march=rv32gc_zve64*. + in the 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. Since we have + VNx1SImode in -march=*zve32* and VNx1DImode in -march=*zve64*, they are + enabled in targetm. vector_mode_supported_p and SLP vectorizer will try to + use them. Currently, we can support auto-vectorization in + -march=rv32_zve32x_zvl128b. Wheras, -march=rv32_zve32x_zvl32b or + -march=rv32_zve32x_zvl64b are disabled. + */ + if (autovec_use_vlmax_p ()) + { + /* If TARGET_MIN_VLEN < 128, we don't allow LMUL < 2 + auto-vectorization since Loop Vectorizer may use VNx1SImode or + VNx1DImode to vectorize which will create ICE in the + 'can_duplicate_and_interleave_p' of tree-vect-slp.cc. */ + if (TARGET_MIN_VLEN < 128 && riscv_autovec_lmul < RVV_M2) + return word_mode; + /* We use LMUL = 1 as base bytesize which is BYTES_PER_RISCV_VECTOR and + riscv_autovec_lmul as multiply factor to calculate the the NUNITS to + get the auto-vectorization mode. */ + poly_uint64 nunits; + poly_uint64 vector_size + = BYTES_PER_RISCV_VECTOR * ((int) riscv_autovec_lmul); + poly_uint64 scalar_size = GET_MODE_SIZE (mode); + if (!multiple_p (vector_size, scalar_size, &nunits)) + return word_mode; + machine_mode rvv_mode; + if (get_vector_mode (mode, nunits).exists (&rvv_mode)) + return rvv_mode; + } + /* TODO: We will support minimum length VLS auto-vectorization in the future. + */ + return word_mode; +} + + } // namespace riscv_vector diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 5d2550871c7..c601389b540 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -6228,7 +6228,15 @@ riscv_convert_vector_bits (void) to set RVV mode size. The RVV machine modes size are run-time constant if TARGET_VECTOR is enabled. The RVV machine modes size remains default compile-time constant if TARGET_VECTOR is disabled. */ - return TARGET_VECTOR ? poly_uint16 (1, 1) : 1; + if (TARGET_VECTOR) + { + if (riscv_autovec_preference == RVV_FIXED_VLMAX) + return (int) TARGET_MIN_VLEN / (riscv_bytes_per_vector_chunk * 8); + else + return poly_uint16 (1, 1); + } + else + return 1; } /* Implement TARGET_OPTION_OVERRIDE. */ @@ -7158,6 +7166,17 @@ riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) & ~zeroed_hardregs); } +/* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */ + +static machine_mode +riscv_preferred_simd_mode (scalar_mode mode) +{ + if (TARGET_VECTOR) + return riscv_vector::preferred_simd_mode (mode); + + return word_mode; +} + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" @@ -7412,6 +7431,9 @@ riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) #undef TARGET_ZERO_CALL_USED_REGS #define TARGET_ZERO_CALL_USED_REGS riscv_zero_call_used_regs +#undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE +#define TARGET_VECTORIZE_PREFERRED_SIMD_MODE riscv_preferred_simd_mode + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-riscv.h" diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 0fda11ed67d..3f06ab574c1 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -23,7 +23,7 @@ ;; This file include : ;; ;; - Intrinsics (https://github.com/riscv/rvv-intrinsic-doc) -;; - Auto-vectorization (TBD) +;; - Auto-vectorization (autovec.md) ;; - Combine optimization (TBD) (include "vector-iterators.md") @@ -7419,3 +7419,5 @@ "vleff.v\t%0,%3%p1" [(set_attr "type" "vldff") (set_attr "mode" "")]) + +(include "autovec.md")