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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id w15-20020a170906d20f00b0094e83bf64e5si13355173ejz.787.2023.04.18.16.33.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 16:33:49 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=e3cTZDa9; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C361D3858002 for ; Tue, 18 Apr 2023 23:33:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C361D3858002 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1681860827; bh=ILRR7PrrLD5oMvzwKxx4mIsegWtmlvREONvnG/eNZMI=; h=To:CC:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=e3cTZDa9TpriVy/tHREQT0ZZ/EgTbOCV1cfwePNf3FJQ/37bYFQH/Lfp3MC0sPO+i 0kWfBO7OdYrMIi2Hmzv7LqjXJ37fiYIC2FHEukuXefoYXtDBsBwAmSMeBOlEyzzo6R w7FUMKYDHlHjVgo4blyIQ9jxPauwzszjym3jV8mc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by sourceware.org (Postfix) with ESMTPS id 8AB403858D1E for ; Tue, 18 Apr 2023 23:33:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8AB403858D1E Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33IJOu0g022741 for ; Tue, 18 Apr 2023 16:33:04 -0700 Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3pyuenu426-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 18 Apr 2023 16:33:03 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 18 Apr 2023 16:33:01 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 18 Apr 2023 16:33:01 -0700 Received: from vpnclient.wrightpinski.org.com (unknown [10.69.242.187]) by maili.marvell.com (Postfix) with ESMTP id 1EEC63F7045; Tue, 18 Apr 2023 16:33:01 -0700 (PDT) To: CC: Andrew Pinski Subject: [PATCH] i386: Add new pattern for zero-extend cmov Date: Tue, 18 Apr 2023 16:32:53 -0700 Message-ID: <20230418233253.293204-1-apinski@marvell.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Proofpoint-GUID: P7b_ycoLo3McyLpTtc-0voxlSaE0aiyB X-Proofpoint-ORIG-GUID: P7b_ycoLo3McyLpTtc-0voxlSaE0aiyB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-18_15,2023-04-18_01,2023-02-09_01 X-Spam-Status: No, score=-14.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrew Pinski via Gcc-patches From: Andrew Pinski Reply-To: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763558900452581092?= X-GMAIL-MSGID: =?utf-8?q?1763558900452581092?= After a phiopt change, I got a failure of cmov9.c. The RTL IR has zero_extend on the outside of the if_then_else rather than on the side. Both ways are considered canonical as mentioned in PR 66588. This fixes the failure I got and also adds a testcase which fails before even my phiopt patch but will pass with this patch. OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions. gcc/ChangeLog: * config/i386/i386.md (*movsicc_noc_zext_1): New pattern. gcc/testsuite/ChangeLog: * gcc.target/i386/cmov10.c: New test. * gcc.target/i386/cmov11.c: New test. --- gcc/config/i386/i386.md | 16 ++++++++++++++++ gcc/testsuite/gcc.target/i386/cmov10.c | 10 ++++++++++ gcc/testsuite/gcc.target/i386/cmov11.c | 10 ++++++++++ 3 files changed, 36 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/cmov10.c create mode 100644 gcc/testsuite/gcc.target/i386/cmov11.c diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 1419ea4cff3..10f15b1e8a8 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -21959,6 +21959,22 @@ (define_insn "*movsicc_noc_zext" [(set_attr "type" "icmov") (set_attr "mode" "SI")]) +(define_insn "*movsicc_noc_zext_1" + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r") + (zero_extend:DI + (if_then_else:SI (match_operator 1 "ix86_comparison_operator" + [(reg FLAGS_REG) (const_int 0)]) + (match_operand:SI 2 "nonimmediate_operand" "rm,0") + (match_operand:SI 3 "nonimmediate_operand" "0,rm"))))] + "TARGET_64BIT + && TARGET_CMOVE && !(MEM_P (operands[2]) && MEM_P (operands[3]))" + "@ + cmov%O2%C1\t{%2, %k0|%k0, %2} + cmov%O2%c1\t{%3, %k0|%k0, %3}" + [(set_attr "type" "icmov") + (set_attr "mode" "SI")]) + + ;; Don't do conditional moves with memory inputs. This splitter helps ;; register starved x86_32 by forcing inputs into registers before reload. (define_split diff --git a/gcc/testsuite/gcc.target/i386/cmov10.c b/gcc/testsuite/gcc.target/i386/cmov10.c new file mode 100644 index 00000000000..9ba23b191fb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/cmov10.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -dp" } */ +/* { dg-final { scan-assembler-not "zero_extendsidi" } } */ + + +void foo (unsigned long long *d, int a, unsigned int b, unsigned int c) +{ + *d = a ? b : c; +} + diff --git a/gcc/testsuite/gcc.target/i386/cmov11.c b/gcc/testsuite/gcc.target/i386/cmov11.c new file mode 100644 index 00000000000..ba8a5e692b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/cmov11.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -dp" } */ +/* { dg-final { scan-assembler-not "zero_extendsidi" } } */ + +unsigned long long foo (int a, unsigned b, unsigned c) +{ + unsigned t = a ? b : c; + return t; +} +