[03/22] arm: [MVE intrinsics] Rework vreinterpretq

Message ID 20230418134608.244751-4-christophe.lyon@arm.com
State Accepted
Headers
Series arm: New framework for MVE intrinsics |

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Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Christophe Lyon April 18, 2023, 1:45 p.m. UTC
  This patch implements vreinterpretq using the new MVE intrinsics
framework.

The old definitions for vreinterpretq are removed as a consequence.

2022-09-08  Murray Steele  <murray.steele@arm.com>
	    Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/arm-mve-builtins-base.cc (vreinterpretq_impl): New class.
	* config/arm/arm-mve-builtins-base.def: Define vreinterpretq.
	* config/arm/arm-mve-builtins-base.h (vreinterpretq): New declaration.
	* config/arm/arm-mve-builtins-shapes.cc (parse_element_type): New function.
	(parse_type): Likewise.
	(parse_signature): Likewise.
	(build_one): Likewise.
	(build_all): Likewise.
	(overloaded_base): New struct.
	(unary_convert_def): Likewise.
	* config/arm/arm-mve-builtins-shapes.h (unary_convert): Declare.
	* config/arm/arm-mve-builtins.cc (TYPES_reinterpret_signed1): New
	macro.
	(TYPES_reinterpret_unsigned1): Likewise.
	(TYPES_reinterpret_integer): Likewise.
	(TYPES_reinterpret_integer1): Likewise.
	(TYPES_reinterpret_float1): Likewise.
	(TYPES_reinterpret_float): Likewise.
	(reinterpret_integer): New.
	(reinterpret_float): New.
	(handle_arm_mve_h): Register builtins.
	* config/arm/arm_mve.h (vreinterpretq_s16): Remove.
	(vreinterpretq_s32): Likewise.
	(vreinterpretq_s64): Likewise.
	(vreinterpretq_s8): Likewise.
	(vreinterpretq_u16): Likewise.
	(vreinterpretq_u32): Likewise.
	(vreinterpretq_u64): Likewise.
	(vreinterpretq_u8): Likewise.
	(vreinterpretq_f16): Likewise.
	(vreinterpretq_f32): Likewise.
	(vreinterpretq_s16_s32): Likewise.
	(vreinterpretq_s16_s64): Likewise.
	(vreinterpretq_s16_s8): Likewise.
	(vreinterpretq_s16_u16): Likewise.
	(vreinterpretq_s16_u32): Likewise.
	(vreinterpretq_s16_u64): Likewise.
	(vreinterpretq_s16_u8): Likewise.
	(vreinterpretq_s32_s16): Likewise.
	(vreinterpretq_s32_s64): Likewise.
	(vreinterpretq_s32_s8): Likewise.
	(vreinterpretq_s32_u16): Likewise.
	(vreinterpretq_s32_u32): Likewise.
	(vreinterpretq_s32_u64): Likewise.
	(vreinterpretq_s32_u8): Likewise.
	(vreinterpretq_s64_s16): Likewise.
	(vreinterpretq_s64_s32): Likewise.
	(vreinterpretq_s64_s8): Likewise.
	(vreinterpretq_s64_u16): Likewise.
	(vreinterpretq_s64_u32): Likewise.
	(vreinterpretq_s64_u64): Likewise.
	(vreinterpretq_s64_u8): Likewise.
	(vreinterpretq_s8_s16): Likewise.
	(vreinterpretq_s8_s32): Likewise.
	(vreinterpretq_s8_s64): Likewise.
	(vreinterpretq_s8_u16): Likewise.
	(vreinterpretq_s8_u32): Likewise.
	(vreinterpretq_s8_u64): Likewise.
	(vreinterpretq_s8_u8): Likewise.
	(vreinterpretq_u16_s16): Likewise.
	(vreinterpretq_u16_s32): Likewise.
	(vreinterpretq_u16_s64): Likewise.
	(vreinterpretq_u16_s8): Likewise.
	(vreinterpretq_u16_u32): Likewise.
	(vreinterpretq_u16_u64): Likewise.
	(vreinterpretq_u16_u8): Likewise.
	(vreinterpretq_u32_s16): Likewise.
	(vreinterpretq_u32_s32): Likewise.
	(vreinterpretq_u32_s64): Likewise.
	(vreinterpretq_u32_s8): Likewise.
	(vreinterpretq_u32_u16): Likewise.
	(vreinterpretq_u32_u64): Likewise.
	(vreinterpretq_u32_u8): Likewise.
	(vreinterpretq_u64_s16): Likewise.
	(vreinterpretq_u64_s32): Likewise.
	(vreinterpretq_u64_s64): Likewise.
	(vreinterpretq_u64_s8): Likewise.
	(vreinterpretq_u64_u16): Likewise.
	(vreinterpretq_u64_u32): Likewise.
	(vreinterpretq_u64_u8): Likewise.
	(vreinterpretq_u8_s16): Likewise.
	(vreinterpretq_u8_s32): Likewise.
	(vreinterpretq_u8_s64): Likewise.
	(vreinterpretq_u8_s8): Likewise.
	(vreinterpretq_u8_u16): Likewise.
	(vreinterpretq_u8_u32): Likewise.
	(vreinterpretq_u8_u64): Likewise.
	(vreinterpretq_s32_f16): Likewise.
	(vreinterpretq_s32_f32): Likewise.
	(vreinterpretq_u16_f16): Likewise.
	(vreinterpretq_u16_f32): Likewise.
	(vreinterpretq_u32_f16): Likewise.
	(vreinterpretq_u32_f32): Likewise.
	(vreinterpretq_u64_f16): Likewise.
	(vreinterpretq_u64_f32): Likewise.
	(vreinterpretq_u8_f16): Likewise.
	(vreinterpretq_u8_f32): Likewise.
	(vreinterpretq_f16_f32): Likewise.
	(vreinterpretq_f16_s16): Likewise.
	(vreinterpretq_f16_s32): Likewise.
	(vreinterpretq_f16_s64): Likewise.
	(vreinterpretq_f16_s8): Likewise.
	(vreinterpretq_f16_u16): Likewise.
	(vreinterpretq_f16_u32): Likewise.
	(vreinterpretq_f16_u64): Likewise.
	(vreinterpretq_f16_u8): Likewise.
	(vreinterpretq_f32_f16): Likewise.
	(vreinterpretq_f32_s16): Likewise.
	(vreinterpretq_f32_s32): Likewise.
	(vreinterpretq_f32_s64): Likewise.
	(vreinterpretq_f32_s8): Likewise.
	(vreinterpretq_f32_u16): Likewise.
	(vreinterpretq_f32_u32): Likewise.
	(vreinterpretq_f32_u64): Likewise.
	(vreinterpretq_f32_u8): Likewise.
	(vreinterpretq_s16_f16): Likewise.
	(vreinterpretq_s16_f32): Likewise.
	(vreinterpretq_s64_f16): Likewise.
	(vreinterpretq_s64_f32): Likewise.
	(vreinterpretq_s8_f16): Likewise.
	(vreinterpretq_s8_f32): Likewise.
	(__arm_vreinterpretq_f16): Likewise.
	(__arm_vreinterpretq_f32): Likewise.
	(__arm_vreinterpretq_s16): Likewise.
	(__arm_vreinterpretq_s32): Likewise.
	(__arm_vreinterpretq_s64): Likewise.
	(__arm_vreinterpretq_s8): Likewise.
	(__arm_vreinterpretq_u16): Likewise.
	(__arm_vreinterpretq_u32): Likewise.
	(__arm_vreinterpretq_u64): Likewise.
	(__arm_vreinterpretq_u8): Likewise.
	* config/arm/arm_mve_types.h (__arm_vreinterpretq_s16_s32): Remove.
	(__arm_vreinterpretq_s16_s64): Likewise.
	(__arm_vreinterpretq_s16_s8): Likewise.
	(__arm_vreinterpretq_s16_u16): Likewise.
	(__arm_vreinterpretq_s16_u32): Likewise.
	(__arm_vreinterpretq_s16_u64): Likewise.
	(__arm_vreinterpretq_s16_u8): Likewise.
	(__arm_vreinterpretq_s32_s16): Likewise.
	(__arm_vreinterpretq_s32_s64): Likewise.
	(__arm_vreinterpretq_s32_s8): Likewise.
	(__arm_vreinterpretq_s32_u16): Likewise.
	(__arm_vreinterpretq_s32_u32): Likewise.
	(__arm_vreinterpretq_s32_u64): Likewise.
	(__arm_vreinterpretq_s32_u8): Likewise.
	(__arm_vreinterpretq_s64_s16): Likewise.
	(__arm_vreinterpretq_s64_s32): Likewise.
	(__arm_vreinterpretq_s64_s8): Likewise.
	(__arm_vreinterpretq_s64_u16): Likewise.
	(__arm_vreinterpretq_s64_u32): Likewise.
	(__arm_vreinterpretq_s64_u64): Likewise.
	(__arm_vreinterpretq_s64_u8): Likewise.
	(__arm_vreinterpretq_s8_s16): Likewise.
	(__arm_vreinterpretq_s8_s32): Likewise.
	(__arm_vreinterpretq_s8_s64): Likewise.
	(__arm_vreinterpretq_s8_u16): Likewise.
	(__arm_vreinterpretq_s8_u32): Likewise.
	(__arm_vreinterpretq_s8_u64): Likewise.
	(__arm_vreinterpretq_s8_u8): Likewise.
	(__arm_vreinterpretq_u16_s16): Likewise.
	(__arm_vreinterpretq_u16_s32): Likewise.
	(__arm_vreinterpretq_u16_s64): Likewise.
	(__arm_vreinterpretq_u16_s8): Likewise.
	(__arm_vreinterpretq_u16_u32): Likewise.
	(__arm_vreinterpretq_u16_u64): Likewise.
	(__arm_vreinterpretq_u16_u8): Likewise.
	(__arm_vreinterpretq_u32_s16): Likewise.
	(__arm_vreinterpretq_u32_s32): Likewise.
	(__arm_vreinterpretq_u32_s64): Likewise.
	(__arm_vreinterpretq_u32_s8): Likewise.
	(__arm_vreinterpretq_u32_u16): Likewise.
	(__arm_vreinterpretq_u32_u64): Likewise.
	(__arm_vreinterpretq_u32_u8): Likewise.
	(__arm_vreinterpretq_u64_s16): Likewise.
	(__arm_vreinterpretq_u64_s32): Likewise.
	(__arm_vreinterpretq_u64_s64): Likewise.
	(__arm_vreinterpretq_u64_s8): Likewise.
	(__arm_vreinterpretq_u64_u16): Likewise.
	(__arm_vreinterpretq_u64_u32): Likewise.
	(__arm_vreinterpretq_u64_u8): Likewise.
	(__arm_vreinterpretq_u8_s16): Likewise.
	(__arm_vreinterpretq_u8_s32): Likewise.
	(__arm_vreinterpretq_u8_s64): Likewise.
	(__arm_vreinterpretq_u8_s8): Likewise.
	(__arm_vreinterpretq_u8_u16): Likewise.
	(__arm_vreinterpretq_u8_u32): Likewise.
	(__arm_vreinterpretq_u8_u64): Likewise.
	(__arm_vreinterpretq_s32_f16): Likewise.
	(__arm_vreinterpretq_s32_f32): Likewise.
	(__arm_vreinterpretq_s16_f16): Likewise.
	(__arm_vreinterpretq_s16_f32): Likewise.
	(__arm_vreinterpretq_s64_f16): Likewise.
	(__arm_vreinterpretq_s64_f32): Likewise.
	(__arm_vreinterpretq_s8_f16): Likewise.
	(__arm_vreinterpretq_s8_f32): Likewise.
	(__arm_vreinterpretq_u16_f16): Likewise.
	(__arm_vreinterpretq_u16_f32): Likewise.
	(__arm_vreinterpretq_u32_f16): Likewise.
	(__arm_vreinterpretq_u32_f32): Likewise.
	(__arm_vreinterpretq_u64_f16): Likewise.
	(__arm_vreinterpretq_u64_f32): Likewise.
	(__arm_vreinterpretq_u8_f16): Likewise.
	(__arm_vreinterpretq_u8_f32): Likewise.
	(__arm_vreinterpretq_f16_f32): Likewise.
	(__arm_vreinterpretq_f16_s16): Likewise.
	(__arm_vreinterpretq_f16_s32): Likewise.
	(__arm_vreinterpretq_f16_s64): Likewise.
	(__arm_vreinterpretq_f16_s8): Likewise.
	(__arm_vreinterpretq_f16_u16): Likewise.
	(__arm_vreinterpretq_f16_u32): Likewise.
	(__arm_vreinterpretq_f16_u64): Likewise.
	(__arm_vreinterpretq_f16_u8): Likewise.
	(__arm_vreinterpretq_f32_f16): Likewise.
	(__arm_vreinterpretq_f32_s16): Likewise.
	(__arm_vreinterpretq_f32_s32): Likewise.
	(__arm_vreinterpretq_f32_s64): Likewise.
	(__arm_vreinterpretq_f32_s8): Likewise.
	(__arm_vreinterpretq_f32_u16): Likewise.
	(__arm_vreinterpretq_f32_u32): Likewise.
	(__arm_vreinterpretq_f32_u64): Likewise.
	(__arm_vreinterpretq_f32_u8): Likewise.
	(__arm_vreinterpretq_s16): Likewise.
	(__arm_vreinterpretq_s32): Likewise.
	(__arm_vreinterpretq_s64): Likewise.
	(__arm_vreinterpretq_s8): Likewise.
	(__arm_vreinterpretq_u16): Likewise.
	(__arm_vreinterpretq_u32): Likewise.
	(__arm_vreinterpretq_u64): Likewise.
	(__arm_vreinterpretq_u8): Likewise.
	(__arm_vreinterpretq_f16): Likewise.
	(__arm_vreinterpretq_f32): Likewise.
	* config/arm/mve.md (@arm_mve_reinterpret<mode>): New pattern.
	* config/arm/unspecs.md: (REINTERPRET): New unspec.

	gcc/testsuite/
	* g++.target/arm/mve.exp: Add general-c++ and general directories.
	* g++.target/arm/mve/general-c++/nomve_fp_1.c: New test.
	* g++.target/arm/mve/general-c++/vreinterpretq_1.C: New test.
	* gcc.target/arm/mve/general-c/nomve_fp_1.c: New test.
	* gcc.target/arm/mve/general-c/vreinterpretq_1.c: New test.
---
 gcc/config/arm/arm-mve-builtins-base.cc       |   29 +
 gcc/config/arm/arm-mve-builtins-base.def      |    2 +
 gcc/config/arm/arm-mve-builtins-base.h        |    2 +
 gcc/config/arm/arm-mve-builtins-shapes.cc     |   28 +
 gcc/config/arm/arm-mve-builtins-shapes.h      |    8 +
 gcc/config/arm/arm-mve-builtins.cc            |   60 +
 gcc/config/arm/arm_mve.h                      |  300 ----
 gcc/config/arm/arm_mve_types.h                | 1365 +----------------
 gcc/config/arm/mve.md                         |   18 +
 gcc/config/arm/unspecs.md                     |    1 +
 gcc/testsuite/g++.target/arm/mve.exp          |    8 +-
 .../arm/mve/general-c++/nomve_fp_1.c          |   15 +
 .../arm/mve/general-c++/vreinterpretq_1.C     |   25 +
 .../gcc.target/arm/mve/general-c/nomve_fp_1.c |   15 +
 .../arm/mve/general-c/vreinterpretq_1.c       |   25 +
 15 files changed, 286 insertions(+), 1615 deletions(-)
 create mode 100644 gcc/testsuite/g++.target/arm/mve/general-c++/nomve_fp_1.c
 create mode 100644 gcc/testsuite/g++.target/arm/mve/general-c++/vreinterpretq_1.C
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/general-c/nomve_fp_1.c
 create mode 100644 gcc/testsuite/gcc.target/arm/mve/general-c/vreinterpretq_1.c
  

Comments

Kyrylo Tkachov May 2, 2023, 10:26 a.m. UTC | #1
Hi Christophe,

> -----Original Message-----
> From: Christophe Lyon <christophe.lyon@arm.com>
> Sent: Tuesday, April 18, 2023 2:46 PM
> To: gcc-patches@gcc.gnu.org; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>;
> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
> <Richard.Sandiford@arm.com>
> Cc: Christophe Lyon <Christophe.Lyon@arm.com>
> Subject: [PATCH 03/22] arm: [MVE intrinsics] Rework vreinterpretq
> 
> This patch implements vreinterpretq using the new MVE intrinsics
> framework.
> 
> The old definitions for vreinterpretq are removed as a consequence.
> 
> 2022-09-08  Murray Steele  <murray.steele@arm.com>
> 	    Christophe Lyon  <christophe.lyon@arm.com>
> 
> 	gcc/
> 	* config/arm/arm-mve-builtins-base.cc (vreinterpretq_impl): New
> class.
> 	* config/arm/arm-mve-builtins-base.def: Define vreinterpretq.
> 	* config/arm/arm-mve-builtins-base.h (vreinterpretq): New
> declaration.
> 	* config/arm/arm-mve-builtins-shapes.cc (parse_element_type): New
> function.
> 	(parse_type): Likewise.
> 	(parse_signature): Likewise.
> 	(build_one): Likewise.
> 	(build_all): Likewise.
> 	(overloaded_base): New struct.
> 	(unary_convert_def): Likewise.
> 	* config/arm/arm-mve-builtins-shapes.h (unary_convert): Declare.
> 	* config/arm/arm-mve-builtins.cc (TYPES_reinterpret_signed1): New
> 	macro.
> 	(TYPES_reinterpret_unsigned1): Likewise.
> 	(TYPES_reinterpret_integer): Likewise.
> 	(TYPES_reinterpret_integer1): Likewise.
> 	(TYPES_reinterpret_float1): Likewise.
> 	(TYPES_reinterpret_float): Likewise.
> 	(reinterpret_integer): New.
> 	(reinterpret_float): New.
> 	(handle_arm_mve_h): Register builtins.
> 	* config/arm/arm_mve.h (vreinterpretq_s16): Remove.
> 	(vreinterpretq_s32): Likewise.
> 	(vreinterpretq_s64): Likewise.
> 	(vreinterpretq_s8): Likewise.
> 	(vreinterpretq_u16): Likewise.
> 	(vreinterpretq_u32): Likewise.
> 	(vreinterpretq_u64): Likewise.
> 	(vreinterpretq_u8): Likewise.
> 	(vreinterpretq_f16): Likewise.
> 	(vreinterpretq_f32): Likewise.
> 	(vreinterpretq_s16_s32): Likewise.
> 	(vreinterpretq_s16_s64): Likewise.
> 	(vreinterpretq_s16_s8): Likewise.
> 	(vreinterpretq_s16_u16): Likewise.
> 	(vreinterpretq_s16_u32): Likewise.
> 	(vreinterpretq_s16_u64): Likewise.
> 	(vreinterpretq_s16_u8): Likewise.
> 	(vreinterpretq_s32_s16): Likewise.
> 	(vreinterpretq_s32_s64): Likewise.
> 	(vreinterpretq_s32_s8): Likewise.
> 	(vreinterpretq_s32_u16): Likewise.
> 	(vreinterpretq_s32_u32): Likewise.
> 	(vreinterpretq_s32_u64): Likewise.
> 	(vreinterpretq_s32_u8): Likewise.
> 	(vreinterpretq_s64_s16): Likewise.
> 	(vreinterpretq_s64_s32): Likewise.
> 	(vreinterpretq_s64_s8): Likewise.
> 	(vreinterpretq_s64_u16): Likewise.
> 	(vreinterpretq_s64_u32): Likewise.
> 	(vreinterpretq_s64_u64): Likewise.
> 	(vreinterpretq_s64_u8): Likewise.
> 	(vreinterpretq_s8_s16): Likewise.
> 	(vreinterpretq_s8_s32): Likewise.
> 	(vreinterpretq_s8_s64): Likewise.
> 	(vreinterpretq_s8_u16): Likewise.
> 	(vreinterpretq_s8_u32): Likewise.
> 	(vreinterpretq_s8_u64): Likewise.
> 	(vreinterpretq_s8_u8): Likewise.
> 	(vreinterpretq_u16_s16): Likewise.
> 	(vreinterpretq_u16_s32): Likewise.
> 	(vreinterpretq_u16_s64): Likewise.
> 	(vreinterpretq_u16_s8): Likewise.
> 	(vreinterpretq_u16_u32): Likewise.
> 	(vreinterpretq_u16_u64): Likewise.
> 	(vreinterpretq_u16_u8): Likewise.
> 	(vreinterpretq_u32_s16): Likewise.
> 	(vreinterpretq_u32_s32): Likewise.
> 	(vreinterpretq_u32_s64): Likewise.
> 	(vreinterpretq_u32_s8): Likewise.
> 	(vreinterpretq_u32_u16): Likewise.
> 	(vreinterpretq_u32_u64): Likewise.
> 	(vreinterpretq_u32_u8): Likewise.
> 	(vreinterpretq_u64_s16): Likewise.
> 	(vreinterpretq_u64_s32): Likewise.
> 	(vreinterpretq_u64_s64): Likewise.
> 	(vreinterpretq_u64_s8): Likewise.
> 	(vreinterpretq_u64_u16): Likewise.
> 	(vreinterpretq_u64_u32): Likewise.
> 	(vreinterpretq_u64_u8): Likewise.
> 	(vreinterpretq_u8_s16): Likewise.
> 	(vreinterpretq_u8_s32): Likewise.
> 	(vreinterpretq_u8_s64): Likewise.
> 	(vreinterpretq_u8_s8): Likewise.
> 	(vreinterpretq_u8_u16): Likewise.
> 	(vreinterpretq_u8_u32): Likewise.
> 	(vreinterpretq_u8_u64): Likewise.
> 	(vreinterpretq_s32_f16): Likewise.
> 	(vreinterpretq_s32_f32): Likewise.
> 	(vreinterpretq_u16_f16): Likewise.
> 	(vreinterpretq_u16_f32): Likewise.
> 	(vreinterpretq_u32_f16): Likewise.
> 	(vreinterpretq_u32_f32): Likewise.
> 	(vreinterpretq_u64_f16): Likewise.
> 	(vreinterpretq_u64_f32): Likewise.
> 	(vreinterpretq_u8_f16): Likewise.
> 	(vreinterpretq_u8_f32): Likewise.
> 	(vreinterpretq_f16_f32): Likewise.
> 	(vreinterpretq_f16_s16): Likewise.
> 	(vreinterpretq_f16_s32): Likewise.
> 	(vreinterpretq_f16_s64): Likewise.
> 	(vreinterpretq_f16_s8): Likewise.
> 	(vreinterpretq_f16_u16): Likewise.
> 	(vreinterpretq_f16_u32): Likewise.
> 	(vreinterpretq_f16_u64): Likewise.
> 	(vreinterpretq_f16_u8): Likewise.
> 	(vreinterpretq_f32_f16): Likewise.
> 	(vreinterpretq_f32_s16): Likewise.
> 	(vreinterpretq_f32_s32): Likewise.
> 	(vreinterpretq_f32_s64): Likewise.
> 	(vreinterpretq_f32_s8): Likewise.
> 	(vreinterpretq_f32_u16): Likewise.
> 	(vreinterpretq_f32_u32): Likewise.
> 	(vreinterpretq_f32_u64): Likewise.
> 	(vreinterpretq_f32_u8): Likewise.
> 	(vreinterpretq_s16_f16): Likewise.
> 	(vreinterpretq_s16_f32): Likewise.
> 	(vreinterpretq_s64_f16): Likewise.
> 	(vreinterpretq_s64_f32): Likewise.
> 	(vreinterpretq_s8_f16): Likewise.
> 	(vreinterpretq_s8_f32): Likewise.
> 	(__arm_vreinterpretq_f16): Likewise.
> 	(__arm_vreinterpretq_f32): Likewise.
> 	(__arm_vreinterpretq_s16): Likewise.
> 	(__arm_vreinterpretq_s32): Likewise.
> 	(__arm_vreinterpretq_s64): Likewise.
> 	(__arm_vreinterpretq_s8): Likewise.
> 	(__arm_vreinterpretq_u16): Likewise.
> 	(__arm_vreinterpretq_u32): Likewise.
> 	(__arm_vreinterpretq_u64): Likewise.
> 	(__arm_vreinterpretq_u8): Likewise.
> 	* config/arm/arm_mve_types.h (__arm_vreinterpretq_s16_s32):
> Remove.
> 	(__arm_vreinterpretq_s16_s64): Likewise.
> 	(__arm_vreinterpretq_s16_s8): Likewise.
> 	(__arm_vreinterpretq_s16_u16): Likewise.
> 	(__arm_vreinterpretq_s16_u32): Likewise.
> 	(__arm_vreinterpretq_s16_u64): Likewise.
> 	(__arm_vreinterpretq_s16_u8): Likewise.
> 	(__arm_vreinterpretq_s32_s16): Likewise.
> 	(__arm_vreinterpretq_s32_s64): Likewise.
> 	(__arm_vreinterpretq_s32_s8): Likewise.
> 	(__arm_vreinterpretq_s32_u16): Likewise.
> 	(__arm_vreinterpretq_s32_u32): Likewise.
> 	(__arm_vreinterpretq_s32_u64): Likewise.
> 	(__arm_vreinterpretq_s32_u8): Likewise.
> 	(__arm_vreinterpretq_s64_s16): Likewise.
> 	(__arm_vreinterpretq_s64_s32): Likewise.
> 	(__arm_vreinterpretq_s64_s8): Likewise.
> 	(__arm_vreinterpretq_s64_u16): Likewise.
> 	(__arm_vreinterpretq_s64_u32): Likewise.
> 	(__arm_vreinterpretq_s64_u64): Likewise.
> 	(__arm_vreinterpretq_s64_u8): Likewise.
> 	(__arm_vreinterpretq_s8_s16): Likewise.
> 	(__arm_vreinterpretq_s8_s32): Likewise.
> 	(__arm_vreinterpretq_s8_s64): Likewise.
> 	(__arm_vreinterpretq_s8_u16): Likewise.
> 	(__arm_vreinterpretq_s8_u32): Likewise.
> 	(__arm_vreinterpretq_s8_u64): Likewise.
> 	(__arm_vreinterpretq_s8_u8): Likewise.
> 	(__arm_vreinterpretq_u16_s16): Likewise.
> 	(__arm_vreinterpretq_u16_s32): Likewise.
> 	(__arm_vreinterpretq_u16_s64): Likewise.
> 	(__arm_vreinterpretq_u16_s8): Likewise.
> 	(__arm_vreinterpretq_u16_u32): Likewise.
> 	(__arm_vreinterpretq_u16_u64): Likewise.
> 	(__arm_vreinterpretq_u16_u8): Likewise.
> 	(__arm_vreinterpretq_u32_s16): Likewise.
> 	(__arm_vreinterpretq_u32_s32): Likewise.
> 	(__arm_vreinterpretq_u32_s64): Likewise.
> 	(__arm_vreinterpretq_u32_s8): Likewise.
> 	(__arm_vreinterpretq_u32_u16): Likewise.
> 	(__arm_vreinterpretq_u32_u64): Likewise.
> 	(__arm_vreinterpretq_u32_u8): Likewise.
> 	(__arm_vreinterpretq_u64_s16): Likewise.
> 	(__arm_vreinterpretq_u64_s32): Likewise.
> 	(__arm_vreinterpretq_u64_s64): Likewise.
> 	(__arm_vreinterpretq_u64_s8): Likewise.
> 	(__arm_vreinterpretq_u64_u16): Likewise.
> 	(__arm_vreinterpretq_u64_u32): Likewise.
> 	(__arm_vreinterpretq_u64_u8): Likewise.
> 	(__arm_vreinterpretq_u8_s16): Likewise.
> 	(__arm_vreinterpretq_u8_s32): Likewise.
> 	(__arm_vreinterpretq_u8_s64): Likewise.
> 	(__arm_vreinterpretq_u8_s8): Likewise.
> 	(__arm_vreinterpretq_u8_u16): Likewise.
> 	(__arm_vreinterpretq_u8_u32): Likewise.
> 	(__arm_vreinterpretq_u8_u64): Likewise.
> 	(__arm_vreinterpretq_s32_f16): Likewise.
> 	(__arm_vreinterpretq_s32_f32): Likewise.
> 	(__arm_vreinterpretq_s16_f16): Likewise.
> 	(__arm_vreinterpretq_s16_f32): Likewise.
> 	(__arm_vreinterpretq_s64_f16): Likewise.
> 	(__arm_vreinterpretq_s64_f32): Likewise.
> 	(__arm_vreinterpretq_s8_f16): Likewise.
> 	(__arm_vreinterpretq_s8_f32): Likewise.
> 	(__arm_vreinterpretq_u16_f16): Likewise.
> 	(__arm_vreinterpretq_u16_f32): Likewise.
> 	(__arm_vreinterpretq_u32_f16): Likewise.
> 	(__arm_vreinterpretq_u32_f32): Likewise.
> 	(__arm_vreinterpretq_u64_f16): Likewise.
> 	(__arm_vreinterpretq_u64_f32): Likewise.
> 	(__arm_vreinterpretq_u8_f16): Likewise.
> 	(__arm_vreinterpretq_u8_f32): Likewise.
> 	(__arm_vreinterpretq_f16_f32): Likewise.
> 	(__arm_vreinterpretq_f16_s16): Likewise.
> 	(__arm_vreinterpretq_f16_s32): Likewise.
> 	(__arm_vreinterpretq_f16_s64): Likewise.
> 	(__arm_vreinterpretq_f16_s8): Likewise.
> 	(__arm_vreinterpretq_f16_u16): Likewise.
> 	(__arm_vreinterpretq_f16_u32): Likewise.
> 	(__arm_vreinterpretq_f16_u64): Likewise.
> 	(__arm_vreinterpretq_f16_u8): Likewise.
> 	(__arm_vreinterpretq_f32_f16): Likewise.
> 	(__arm_vreinterpretq_f32_s16): Likewise.
> 	(__arm_vreinterpretq_f32_s32): Likewise.
> 	(__arm_vreinterpretq_f32_s64): Likewise.
> 	(__arm_vreinterpretq_f32_s8): Likewise.
> 	(__arm_vreinterpretq_f32_u16): Likewise.
> 	(__arm_vreinterpretq_f32_u32): Likewise.
> 	(__arm_vreinterpretq_f32_u64): Likewise.
> 	(__arm_vreinterpretq_f32_u8): Likewise.
> 	(__arm_vreinterpretq_s16): Likewise.
> 	(__arm_vreinterpretq_s32): Likewise.
> 	(__arm_vreinterpretq_s64): Likewise.
> 	(__arm_vreinterpretq_s8): Likewise.
> 	(__arm_vreinterpretq_u16): Likewise.
> 	(__arm_vreinterpretq_u32): Likewise.
> 	(__arm_vreinterpretq_u64): Likewise.
> 	(__arm_vreinterpretq_u8): Likewise.
> 	(__arm_vreinterpretq_f16): Likewise.
> 	(__arm_vreinterpretq_f32): Likewise.
> 	* config/arm/mve.md (@arm_mve_reinterpret<mode>): New
> pattern.
> 	* config/arm/unspecs.md: (REINTERPRET): New unspec.
> 
> 	gcc/testsuite/
> 	* g++.target/arm/mve.exp: Add general-c++ and general directories.
> 	* g++.target/arm/mve/general-c++/nomve_fp_1.c: New test.
> 	* g++.target/arm/mve/general-c++/vreinterpretq_1.C: New test.
> 	* gcc.target/arm/mve/general-c/nomve_fp_1.c: New test.
> 	* gcc.target/arm/mve/general-c/vreinterpretq_1.c: New test.
> ---
>  gcc/config/arm/arm-mve-builtins-base.cc       |   29 +
>  gcc/config/arm/arm-mve-builtins-base.def      |    2 +
>  gcc/config/arm/arm-mve-builtins-base.h        |    2 +
>  gcc/config/arm/arm-mve-builtins-shapes.cc     |   28 +
>  gcc/config/arm/arm-mve-builtins-shapes.h      |    8 +
>  gcc/config/arm/arm-mve-builtins.cc            |   60 +
>  gcc/config/arm/arm_mve.h                      |  300 ----
>  gcc/config/arm/arm_mve_types.h                | 1365 +----------------
>  gcc/config/arm/mve.md                         |   18 +
>  gcc/config/arm/unspecs.md                     |    1 +
>  gcc/testsuite/g++.target/arm/mve.exp          |    8 +-
>  .../arm/mve/general-c++/nomve_fp_1.c          |   15 +
>  .../arm/mve/general-c++/vreinterpretq_1.C     |   25 +
>  .../gcc.target/arm/mve/general-c/nomve_fp_1.c |   15 +
>  .../arm/mve/general-c/vreinterpretq_1.c       |   25 +
>  15 files changed, 286 insertions(+), 1615 deletions(-)
>  create mode 100644 gcc/testsuite/g++.target/arm/mve/general-
> c++/nomve_fp_1.c
>  create mode 100644 gcc/testsuite/g++.target/arm/mve/general-
> c++/vreinterpretq_1.C
>  create mode 100644 gcc/testsuite/gcc.target/arm/mve/general-
> c/nomve_fp_1.c
>  create mode 100644 gcc/testsuite/gcc.target/arm/mve/general-
> c/vreinterpretq_1.c
> 
> diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-
> mve-builtins-base.cc
> index e9f285faf2b..ad8d500afc6 100644
> --- a/gcc/config/arm/arm-mve-builtins-base.cc
> +++ b/gcc/config/arm/arm-mve-builtins-base.cc
> @@ -38,8 +38,37 @@ using namespace arm_mve;
> 
>  namespace {
> 
> +/* Implements vreinterpretq_* intrinsics.  */
> +class vreinterpretq_impl : public quiet<function_base>
> +{
> +  gimple *
> +  fold (gimple_folder &f) const override
> +  {
> +    /* Punt to rtl if the effect of the reinterpret on registers does not
> +       conform to GCC's endianness model.  */
> +    if (!targetm.can_change_mode_class (f.vector_mode (0),
> +					f.vector_mode (1), VFP_REGS))
> +      return NULL;
> +

So we punt to an RTL pattern here if we cannot change mode class...

[snip]

> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> index 35eab6c94bf..ab688396f97 100644
> --- a/gcc/config/arm/mve.md
> +++ b/gcc/config/arm/mve.md
> @@ -10561,3 +10561,21 @@ (define_expand
> "vcond_mask_<mode><MVE_vpred>"
>      }
>    DONE;
>  })
> +
> +;; Reinterpret operand 1 in operand 0's mode, without changing its contents.
> +(define_expand "@arm_mve_reinterpret<mode>"
> +  [(set (match_operand:MVE_vecs 0 "register_operand")
> +	(unspec:MVE_vecs
> +	  [(match_operand 1 "arm_any_register_operand")]
> +	  REINTERPRET))]
> +  "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
> +    || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE
> (<MODE>mode))"
> +  {
> +    machine_mode src_mode = GET_MODE (operands[1]);
> +    if (targetm.can_change_mode_class (<MODE>mode, src_mode,
> VFP_REGS))
> +      {
> +	emit_move_insn (operands[0], gen_lowpart (<MODE>mode,
> operands[1]));
> +	DONE;
> +      }
> +  }
> +)

... But we still check can_change_mode_class in this pattern and if it's not true we emit the new REINTERPRET unspec
without a corresponding define_insn pattern. Won't that ICE? Would this case occur on big-endian targets?

Thanks,
Kyrill

> diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
> index 84384ee798d..dccda283573 100644
> --- a/gcc/config/arm/unspecs.md
> +++ b/gcc/config/arm/unspecs.md
> @@ -1255,4 +1255,5 @@ (define_c_enum "unspec" [
>    SQRSHRL_64
>    SQRSHRL_48
>    VSHLCQ_M_
> +  REINTERPRET
>  ])
  
Christophe Lyon May 2, 2023, 2:05 p.m. UTC | #2
On 5/2/23 12:26, Kyrylo Tkachov wrote:
> Hi Christophe,
>
>> -----Original Message-----
>> From: Christophe Lyon<christophe.lyon@arm.com>
>> Sent: Tuesday, April 18, 2023 2:46 PM
>> To:gcc-patches@gcc.gnu.org; Kyrylo Tkachov<Kyrylo.Tkachov@arm.com>;
>> Richard Earnshaw<Richard.Earnshaw@arm.com>; Richard Sandiford
>> <Richard.Sandiford@arm.com>
>> Cc: Christophe Lyon<Christophe.Lyon@arm.com>
>> Subject: [PATCH 03/22] arm: [MVE intrinsics] Rework vreinterpretq
>>
>> This patch implements vreinterpretq using the new MVE intrinsics
>> framework.
>>
>> The old definitions for vreinterpretq are removed as a consequence.
>>
>> 2022-09-08  Murray Steele<murray.steele@arm.com>
>> 	    Christophe Lyon<christophe.lyon@arm.com>
>>
>> 	gcc/
>> 	* config/arm/arm-mve-builtins-base.cc (vreinterpretq_impl): New
>> class.
>> 	* config/arm/arm-mve-builtins-base.def: Define vreinterpretq.
>> 	* config/arm/arm-mve-builtins-base.h (vreinterpretq): New
>> declaration.
>> 	* config/arm/arm-mve-builtins-shapes.cc (parse_element_type): New
>> function.
>> 	(parse_type): Likewise.
>> 	(parse_signature): Likewise.
>> 	(build_one): Likewise.
>> 	(build_all): Likewise.
>> 	(overloaded_base): New struct.
>> 	(unary_convert_def): Likewise.
>> 	* config/arm/arm-mve-builtins-shapes.h (unary_convert): Declare.
>> 	* config/arm/arm-mve-builtins.cc (TYPES_reinterpret_signed1): New
>> 	macro.
>> 	(TYPES_reinterpret_unsigned1): Likewise.
>> 	(TYPES_reinterpret_integer): Likewise.
>> 	(TYPES_reinterpret_integer1): Likewise.
>> 	(TYPES_reinterpret_float1): Likewise.
>> 	(TYPES_reinterpret_float): Likewise.
>> 	(reinterpret_integer): New.
>> 	(reinterpret_float): New.
>> 	(handle_arm_mve_h): Register builtins.
>> 	* config/arm/arm_mve.h (vreinterpretq_s16): Remove.
>> 	(vreinterpretq_s32): Likewise.
>> 	(vreinterpretq_s64): Likewise.
>> 	(vreinterpretq_s8): Likewise.
>> 	(vreinterpretq_u16): Likewise.
>> 	(vreinterpretq_u32): Likewise.
>> 	(vreinterpretq_u64): Likewise.
>> 	(vreinterpretq_u8): Likewise.
>> 	(vreinterpretq_f16): Likewise.
>> 	(vreinterpretq_f32): Likewise.
>> 	(vreinterpretq_s16_s32): Likewise.
>> 	(vreinterpretq_s16_s64): Likewise.
>> 	(vreinterpretq_s16_s8): Likewise.
>> 	(vreinterpretq_s16_u16): Likewise.
>> 	(vreinterpretq_s16_u32): Likewise.
>> 	(vreinterpretq_s16_u64): Likewise.
>> 	(vreinterpretq_s16_u8): Likewise.
>> 	(vreinterpretq_s32_s16): Likewise.
>> 	(vreinterpretq_s32_s64): Likewise.
>> 	(vreinterpretq_s32_s8): Likewise.
>> 	(vreinterpretq_s32_u16): Likewise.
>> 	(vreinterpretq_s32_u32): Likewise.
>> 	(vreinterpretq_s32_u64): Likewise.
>> 	(vreinterpretq_s32_u8): Likewise.
>> 	(vreinterpretq_s64_s16): Likewise.
>> 	(vreinterpretq_s64_s32): Likewise.
>> 	(vreinterpretq_s64_s8): Likewise.
>> 	(vreinterpretq_s64_u16): Likewise.
>> 	(vreinterpretq_s64_u32): Likewise.
>> 	(vreinterpretq_s64_u64): Likewise.
>> 	(vreinterpretq_s64_u8): Likewise.
>> 	(vreinterpretq_s8_s16): Likewise.
>> 	(vreinterpretq_s8_s32): Likewise.
>> 	(vreinterpretq_s8_s64): Likewise.
>> 	(vreinterpretq_s8_u16): Likewise.
>> 	(vreinterpretq_s8_u32): Likewise.
>> 	(vreinterpretq_s8_u64): Likewise.
>> 	(vreinterpretq_s8_u8): Likewise.
>> 	(vreinterpretq_u16_s16): Likewise.
>> 	(vreinterpretq_u16_s32): Likewise.
>> 	(vreinterpretq_u16_s64): Likewise.
>> 	(vreinterpretq_u16_s8): Likewise.
>> 	(vreinterpretq_u16_u32): Likewise.
>> 	(vreinterpretq_u16_u64): Likewise.
>> 	(vreinterpretq_u16_u8): Likewise.
>> 	(vreinterpretq_u32_s16): Likewise.
>> 	(vreinterpretq_u32_s32): Likewise.
>> 	(vreinterpretq_u32_s64): Likewise.
>> 	(vreinterpretq_u32_s8): Likewise.
>> 	(vreinterpretq_u32_u16): Likewise.
>> 	(vreinterpretq_u32_u64): Likewise.
>> 	(vreinterpretq_u32_u8): Likewise.
>> 	(vreinterpretq_u64_s16): Likewise.
>> 	(vreinterpretq_u64_s32): Likewise.
>> 	(vreinterpretq_u64_s64): Likewise.
>> 	(vreinterpretq_u64_s8): Likewise.
>> 	(vreinterpretq_u64_u16): Likewise.
>> 	(vreinterpretq_u64_u32): Likewise.
>> 	(vreinterpretq_u64_u8): Likewise.
>> 	(vreinterpretq_u8_s16): Likewise.
>> 	(vreinterpretq_u8_s32): Likewise.
>> 	(vreinterpretq_u8_s64): Likewise.
>> 	(vreinterpretq_u8_s8): Likewise.
>> 	(vreinterpretq_u8_u16): Likewise.
>> 	(vreinterpretq_u8_u32): Likewise.
>> 	(vreinterpretq_u8_u64): Likewise.
>> 	(vreinterpretq_s32_f16): Likewise.
>> 	(vreinterpretq_s32_f32): Likewise.
>> 	(vreinterpretq_u16_f16): Likewise.
>> 	(vreinterpretq_u16_f32): Likewise.
>> 	(vreinterpretq_u32_f16): Likewise.
>> 	(vreinterpretq_u32_f32): Likewise.
>> 	(vreinterpretq_u64_f16): Likewise.
>> 	(vreinterpretq_u64_f32): Likewise.
>> 	(vreinterpretq_u8_f16): Likewise.
>> 	(vreinterpretq_u8_f32): Likewise.
>> 	(vreinterpretq_f16_f32): Likewise.
>> 	(vreinterpretq_f16_s16): Likewise.
>> 	(vreinterpretq_f16_s32): Likewise.
>> 	(vreinterpretq_f16_s64): Likewise.
>> 	(vreinterpretq_f16_s8): Likewise.
>> 	(vreinterpretq_f16_u16): Likewise.
>> 	(vreinterpretq_f16_u32): Likewise.
>> 	(vreinterpretq_f16_u64): Likewise.
>> 	(vreinterpretq_f16_u8): Likewise.
>> 	(vreinterpretq_f32_f16): Likewise.
>> 	(vreinterpretq_f32_s16): Likewise.
>> 	(vreinterpretq_f32_s32): Likewise.
>> 	(vreinterpretq_f32_s64): Likewise.
>> 	(vreinterpretq_f32_s8): Likewise.
>> 	(vreinterpretq_f32_u16): Likewise.
>> 	(vreinterpretq_f32_u32): Likewise.
>> 	(vreinterpretq_f32_u64): Likewise.
>> 	(vreinterpretq_f32_u8): Likewise.
>> 	(vreinterpretq_s16_f16): Likewise.
>> 	(vreinterpretq_s16_f32): Likewise.
>> 	(vreinterpretq_s64_f16): Likewise.
>> 	(vreinterpretq_s64_f32): Likewise.
>> 	(vreinterpretq_s8_f16): Likewise.
>> 	(vreinterpretq_s8_f32): Likewise.
>> 	(__arm_vreinterpretq_f16): Likewise.
>> 	(__arm_vreinterpretq_f32): Likewise.
>> 	(__arm_vreinterpretq_s16): Likewise.
>> 	(__arm_vreinterpretq_s32): Likewise.
>> 	(__arm_vreinterpretq_s64): Likewise.
>> 	(__arm_vreinterpretq_s8): Likewise.
>> 	(__arm_vreinterpretq_u16): Likewise.
>> 	(__arm_vreinterpretq_u32): Likewise.
>> 	(__arm_vreinterpretq_u64): Likewise.
>> 	(__arm_vreinterpretq_u8): Likewise.
>> 	* config/arm/arm_mve_types.h (__arm_vreinterpretq_s16_s32):
>> Remove.
>> 	(__arm_vreinterpretq_s16_s64): Likewise.
>> 	(__arm_vreinterpretq_s16_s8): Likewise.
>> 	(__arm_vreinterpretq_s16_u16): Likewise.
>> 	(__arm_vreinterpretq_s16_u32): Likewise.
>> 	(__arm_vreinterpretq_s16_u64): Likewise.
>> 	(__arm_vreinterpretq_s16_u8): Likewise.
>> 	(__arm_vreinterpretq_s32_s16): Likewise.
>> 	(__arm_vreinterpretq_s32_s64): Likewise.
>> 	(__arm_vreinterpretq_s32_s8): Likewise.
>> 	(__arm_vreinterpretq_s32_u16): Likewise.
>> 	(__arm_vreinterpretq_s32_u32): Likewise.
>> 	(__arm_vreinterpretq_s32_u64): Likewise.
>> 	(__arm_vreinterpretq_s32_u8): Likewise.
>> 	(__arm_vreinterpretq_s64_s16): Likewise.
>> 	(__arm_vreinterpretq_s64_s32): Likewise.
>> 	(__arm_vreinterpretq_s64_s8): Likewise.
>> 	(__arm_vreinterpretq_s64_u16): Likewise.
>> 	(__arm_vreinterpretq_s64_u32): Likewise.
>> 	(__arm_vreinterpretq_s64_u64): Likewise.
>> 	(__arm_vreinterpretq_s64_u8): Likewise.
>> 	(__arm_vreinterpretq_s8_s16): Likewise.
>> 	(__arm_vreinterpretq_s8_s32): Likewise.
>> 	(__arm_vreinterpretq_s8_s64): Likewise.
>> 	(__arm_vreinterpretq_s8_u16): Likewise.
>> 	(__arm_vreinterpretq_s8_u32): Likewise.
>> 	(__arm_vreinterpretq_s8_u64): Likewise.
>> 	(__arm_vreinterpretq_s8_u8): Likewise.
>> 	(__arm_vreinterpretq_u16_s16): Likewise.
>> 	(__arm_vreinterpretq_u16_s32): Likewise.
>> 	(__arm_vreinterpretq_u16_s64): Likewise.
>> 	(__arm_vreinterpretq_u16_s8): Likewise.
>> 	(__arm_vreinterpretq_u16_u32): Likewise.
>> 	(__arm_vreinterpretq_u16_u64): Likewise.
>> 	(__arm_vreinterpretq_u16_u8): Likewise.
>> 	(__arm_vreinterpretq_u32_s16): Likewise.
>> 	(__arm_vreinterpretq_u32_s32): Likewise.
>> 	(__arm_vreinterpretq_u32_s64): Likewise.
>> 	(__arm_vreinterpretq_u32_s8): Likewise.
>> 	(__arm_vreinterpretq_u32_u16): Likewise.
>> 	(__arm_vreinterpretq_u32_u64): Likewise.
>> 	(__arm_vreinterpretq_u32_u8): Likewise.
>> 	(__arm_vreinterpretq_u64_s16): Likewise.
>> 	(__arm_vreinterpretq_u64_s32): Likewise.
>> 	(__arm_vreinterpretq_u64_s64): Likewise.
>> 	(__arm_vreinterpretq_u64_s8): Likewise.
>> 	(__arm_vreinterpretq_u64_u16): Likewise.
>> 	(__arm_vreinterpretq_u64_u32): Likewise.
>> 	(__arm_vreinterpretq_u64_u8): Likewise.
>> 	(__arm_vreinterpretq_u8_s16): Likewise.
>> 	(__arm_vreinterpretq_u8_s32): Likewise.
>> 	(__arm_vreinterpretq_u8_s64): Likewise.
>> 	(__arm_vreinterpretq_u8_s8): Likewise.
>> 	(__arm_vreinterpretq_u8_u16): Likewise.
>> 	(__arm_vreinterpretq_u8_u32): Likewise.
>> 	(__arm_vreinterpretq_u8_u64): Likewise.
>> 	(__arm_vreinterpretq_s32_f16): Likewise.
>> 	(__arm_vreinterpretq_s32_f32): Likewise.
>> 	(__arm_vreinterpretq_s16_f16): Likewise.
>> 	(__arm_vreinterpretq_s16_f32): Likewise.
>> 	(__arm_vreinterpretq_s64_f16): Likewise.
>> 	(__arm_vreinterpretq_s64_f32): Likewise.
>> 	(__arm_vreinterpretq_s8_f16): Likewise.
>> 	(__arm_vreinterpretq_s8_f32): Likewise.
>> 	(__arm_vreinterpretq_u16_f16): Likewise.
>> 	(__arm_vreinterpretq_u16_f32): Likewise.
>> 	(__arm_vreinterpretq_u32_f16): Likewise.
>> 	(__arm_vreinterpretq_u32_f32): Likewise.
>> 	(__arm_vreinterpretq_u64_f16): Likewise.
>> 	(__arm_vreinterpretq_u64_f32): Likewise.
>> 	(__arm_vreinterpretq_u8_f16): Likewise.
>> 	(__arm_vreinterpretq_u8_f32): Likewise.
>> 	(__arm_vreinterpretq_f16_f32): Likewise.
>> 	(__arm_vreinterpretq_f16_s16): Likewise.
>> 	(__arm_vreinterpretq_f16_s32): Likewise.
>> 	(__arm_vreinterpretq_f16_s64): Likewise.
>> 	(__arm_vreinterpretq_f16_s8): Likewise.
>> 	(__arm_vreinterpretq_f16_u16): Likewise.
>> 	(__arm_vreinterpretq_f16_u32): Likewise.
>> 	(__arm_vreinterpretq_f16_u64): Likewise.
>> 	(__arm_vreinterpretq_f16_u8): Likewise.
>> 	(__arm_vreinterpretq_f32_f16): Likewise.
>> 	(__arm_vreinterpretq_f32_s16): Likewise.
>> 	(__arm_vreinterpretq_f32_s32): Likewise.
>> 	(__arm_vreinterpretq_f32_s64): Likewise.
>> 	(__arm_vreinterpretq_f32_s8): Likewise.
>> 	(__arm_vreinterpretq_f32_u16): Likewise.
>> 	(__arm_vreinterpretq_f32_u32): Likewise.
>> 	(__arm_vreinterpretq_f32_u64): Likewise.
>> 	(__arm_vreinterpretq_f32_u8): Likewise.
>> 	(__arm_vreinterpretq_s16): Likewise.
>> 	(__arm_vreinterpretq_s32): Likewise.
>> 	(__arm_vreinterpretq_s64): Likewise.
>> 	(__arm_vreinterpretq_s8): Likewise.
>> 	(__arm_vreinterpretq_u16): Likewise.
>> 	(__arm_vreinterpretq_u32): Likewise.
>> 	(__arm_vreinterpretq_u64): Likewise.
>> 	(__arm_vreinterpretq_u8): Likewise.
>> 	(__arm_vreinterpretq_f16): Likewise.
>> 	(__arm_vreinterpretq_f32): Likewise.
>> 	* config/arm/mve.md (@arm_mve_reinterpret<mode>): New
>> pattern.
>> 	* config/arm/unspecs.md: (REINTERPRET): New unspec.
>>
>> 	gcc/testsuite/
>> 	* g++.target/arm/mve.exp: Add general-c++ and general directories.
>> 	* g++.target/arm/mve/general-c++/nomve_fp_1.c: New test.
>> 	* g++.target/arm/mve/general-c++/vreinterpretq_1.C: New test.
>> 	* gcc.target/arm/mve/general-c/nomve_fp_1.c: New test.
>> 	* gcc.target/arm/mve/general-c/vreinterpretq_1.c: New test.
>> ---
>>   gcc/config/arm/arm-mve-builtins-base.cc       |   29 +
>>   gcc/config/arm/arm-mve-builtins-base.def      |    2 +
>>   gcc/config/arm/arm-mve-builtins-base.h        |    2 +
>>   gcc/config/arm/arm-mve-builtins-shapes.cc     |   28 +
>>   gcc/config/arm/arm-mve-builtins-shapes.h      |    8 +
>>   gcc/config/arm/arm-mve-builtins.cc            |   60 +
>>   gcc/config/arm/arm_mve.h                      |  300 ----
>>   gcc/config/arm/arm_mve_types.h                | 1365 +----------------
>>   gcc/config/arm/mve.md                         |   18 +
>>   gcc/config/arm/unspecs.md                     |    1 +
>>   gcc/testsuite/g++.target/arm/mve.exp          |    8 +-
>>   .../arm/mve/general-c++/nomve_fp_1.c          |   15 +
>>   .../arm/mve/general-c++/vreinterpretq_1.C     |   25 +
>>   .../gcc.target/arm/mve/general-c/nomve_fp_1.c |   15 +
>>   .../arm/mve/general-c/vreinterpretq_1.c       |   25 +
>>   15 files changed, 286 insertions(+), 1615 deletions(-)
>>   create mode 100644 gcc/testsuite/g++.target/arm/mve/general-
>> c++/nomve_fp_1.c
>>   create mode 100644 gcc/testsuite/g++.target/arm/mve/general-
>> c++/vreinterpretq_1.C
>>   create mode 100644 gcc/testsuite/gcc.target/arm/mve/general-
>> c/nomve_fp_1.c
>>   create mode 100644 gcc/testsuite/gcc.target/arm/mve/general-
>> c/vreinterpretq_1.c
>>
>> diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-
>> mve-builtins-base.cc
>> index e9f285faf2b..ad8d500afc6 100644
>> --- a/gcc/config/arm/arm-mve-builtins-base.cc
>> +++ b/gcc/config/arm/arm-mve-builtins-base.cc
>> @@ -38,8 +38,37 @@ using namespace arm_mve;
>>
>>   namespace {
>>
>> +/* Implements vreinterpretq_* intrinsics.  */
>> +class vreinterpretq_impl : public quiet<function_base>
>> +{
>> +  gimple *
>> +  fold (gimple_folder &f) const override
>> +  {
>> +    /* Punt to rtl if the effect of the reinterpret on registers does not
>> +       conform to GCC's endianness model.  */
>> +    if (!targetm.can_change_mode_class (f.vector_mode (0),
>> +					f.vector_mode (1), VFP_REGS))
>> +      return NULL;
>> +
> So we punt to an RTL pattern here if we cannot change mode class...
>
> [snip]
>
>> diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
>> index 35eab6c94bf..ab688396f97 100644
>> --- a/gcc/config/arm/mve.md
>> +++ b/gcc/config/arm/mve.md
>> @@ -10561,3 +10561,21 @@ (define_expand
>> "vcond_mask_<mode><MVE_vpred>"
>>       }
>>     DONE;
>>   })
>> +
>> +;; Reinterpret operand 1 in operand 0's mode, without changing its contents.
>> +(define_expand "@arm_mve_reinterpret<mode>"
>> +  [(set (match_operand:MVE_vecs 0 "register_operand")
>> +	(unspec:MVE_vecs
>> +	  [(match_operand 1 "arm_any_register_operand")]
>> +	  REINTERPRET))]
>> +  "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
>> +    || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE
>> (<MODE>mode))"
>> +  {
>> +    machine_mode src_mode = GET_MODE (operands[1]);
>> +    if (targetm.can_change_mode_class (<MODE>mode, src_mode,
>> VFP_REGS))
>> +      {
>> +	emit_move_insn (operands[0], gen_lowpart (<MODE>mode,
>> operands[1]));
>> +	DONE;
>> +      }
>> +  }
>> +)
> ... But we still check can_change_mode_class in this pattern and if it's not true we emit the new REINTERPRET unspec
> without a corresponding define_insn pattern. Won't that ICE? Would this case occur on big-endian targets?


Looks like you are right. However, arm_mve.h is protected by:

#if __ARM_BIG_ENDIAN

#error "MVE intrinsics are not supported in Big-Endian mode."


Just tried to hack my arm_mve.h to accept big-endian, and indeed we do ICE.


In fact, this pattern and vreinterpretq_impl above are quite similar to 
the aarch64 implementation.

I tried with a sample

svint16_t foo(svint8_t value1)
{
returnsvreinterpret_s16_s8(value1);
}
and it seems aarch64-none-elf-gcc -march=armv8.2-a+sve -mbig-endian is 
OK, although
aarch64_can_change_mode_class() has:
if (BYTES_BIG_ENDIAN)
...
if (from_sve_p && GET_MODE_UNIT_SIZE (from) != GET_MODE_UNIT_SIZE (to))
return false;
so it should have a similar problem? I', not sure why it doesn't ICE?
Thanks,
Christophe

>
> Thanks,
> Kyrill
>
>> diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
>> index 84384ee798d..dccda283573 100644
>> --- a/gcc/config/arm/unspecs.md
>> +++ b/gcc/config/arm/unspecs.md
>> @@ -1255,4 +1255,5 @@ (define_c_enum "unspec" [
>>     SQRSHRL_64
>>     SQRSHRL_48
>>     VSHLCQ_M_
>> +  REINTERPRET
>>   ])
  
Kyrylo Tkachov May 2, 2023, 3:28 p.m. UTC | #3
> -----Original Message-----
> From: Christophe Lyon <Christophe.Lyon@arm.com>
> Sent: Tuesday, May 2, 2023 3:05 PM
> To: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; gcc-patches@gcc.gnu.org;
> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
> <Richard.Sandiford@arm.com>
> Subject: Re: [PATCH 03/22] arm: [MVE intrinsics] Rework vreinterpretq
> 
> 
> 
> 
> On 5/2/23 12:26, Kyrylo Tkachov wrote:
> 
> 
> 	Hi Christophe,
> 
> 
> 		-----Original Message-----
> 		From: Christophe Lyon <christophe.lyon@arm.com>
> <mailto:christophe.lyon@arm.com>
> 		Sent: Tuesday, April 18, 2023 2:46 PM
> 		To: gcc-patches@gcc.gnu.org <mailto:gcc-
> patches@gcc.gnu.org> ; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
> <mailto:Kyrylo.Tkachov@arm.com> ;
> 		Richard Earnshaw <Richard.Earnshaw@arm.com>
> <mailto:Richard.Earnshaw@arm.com> ; Richard Sandiford
> 		<Richard.Sandiford@arm.com>
> <mailto:Richard.Sandiford@arm.com>
> 		Cc: Christophe Lyon <Christophe.Lyon@arm.com>
> <mailto:Christophe.Lyon@arm.com>
> 		Subject: [PATCH 03/22] arm: [MVE intrinsics] Rework
> vreinterpretq
> 
> 		This patch implements vreinterpretq using the new MVE
> intrinsics
> 		framework.
> 
> 		The old definitions for vreinterpretq are removed as a
> consequence.
> 
> 		2022-09-08  Murray Steele  <murray.steele@arm.com>
> <mailto:murray.steele@arm.com>
> 			    Christophe Lyon  <christophe.lyon@arm.com>
> <mailto:christophe.lyon@arm.com>
> 
> 			gcc/
> 			* config/arm/arm-mve-builtins-base.cc
> (vreinterpretq_impl): New
> 		class.
> 			* config/arm/arm-mve-builtins-base.def: Define
> vreinterpretq.
> 			* config/arm/arm-mve-builtins-base.h
> (vreinterpretq): New
> 		declaration.
> 			* config/arm/arm-mve-builtins-shapes.cc
> (parse_element_type): New
> 		function.
> 			(parse_type): Likewise.
> 			(parse_signature): Likewise.
> 			(build_one): Likewise.
> 			(build_all): Likewise.
> 			(overloaded_base): New struct.
> 			(unary_convert_def): Likewise.
> 			* config/arm/arm-mve-builtins-shapes.h
> (unary_convert): Declare.
> 			* config/arm/arm-mve-builtins.cc
> (TYPES_reinterpret_signed1): New
> 			macro.
> 			(TYPES_reinterpret_unsigned1): Likewise.
> 			(TYPES_reinterpret_integer): Likewise.
> 			(TYPES_reinterpret_integer1): Likewise.
> 			(TYPES_reinterpret_float1): Likewise.
> 			(TYPES_reinterpret_float): Likewise.
> 			(reinterpret_integer): New.
> 			(reinterpret_float): New.
> 			(handle_arm_mve_h): Register builtins.
> 			* config/arm/arm_mve.h (vreinterpretq_s16):
> Remove.
> 			(vreinterpretq_s32): Likewise.
> 			(vreinterpretq_s64): Likewise.
> 			(vreinterpretq_s8): Likewise.
> 			(vreinterpretq_u16): Likewise.
> 			(vreinterpretq_u32): Likewise.
> 			(vreinterpretq_u64): Likewise.
> 			(vreinterpretq_u8): Likewise.
> 			(vreinterpretq_f16): Likewise.
> 			(vreinterpretq_f32): Likewise.
> 			(vreinterpretq_s16_s32): Likewise.
> 			(vreinterpretq_s16_s64): Likewise.
> 			(vreinterpretq_s16_s8): Likewise.
> 			(vreinterpretq_s16_u16): Likewise.
> 			(vreinterpretq_s16_u32): Likewise.
> 			(vreinterpretq_s16_u64): Likewise.
> 			(vreinterpretq_s16_u8): Likewise.
> 			(vreinterpretq_s32_s16): Likewise.
> 			(vreinterpretq_s32_s64): Likewise.
> 			(vreinterpretq_s32_s8): Likewise.
> 			(vreinterpretq_s32_u16): Likewise.
> 			(vreinterpretq_s32_u32): Likewise.
> 			(vreinterpretq_s32_u64): Likewise.
> 			(vreinterpretq_s32_u8): Likewise.
> 			(vreinterpretq_s64_s16): Likewise.
> 			(vreinterpretq_s64_s32): Likewise.
> 			(vreinterpretq_s64_s8): Likewise.
> 			(vreinterpretq_s64_u16): Likewise.
> 			(vreinterpretq_s64_u32): Likewise.
> 			(vreinterpretq_s64_u64): Likewise.
> 			(vreinterpretq_s64_u8): Likewise.
> 			(vreinterpretq_s8_s16): Likewise.
> 			(vreinterpretq_s8_s32): Likewise.
> 			(vreinterpretq_s8_s64): Likewise.
> 			(vreinterpretq_s8_u16): Likewise.
> 			(vreinterpretq_s8_u32): Likewise.
> 			(vreinterpretq_s8_u64): Likewise.
> 			(vreinterpretq_s8_u8): Likewise.
> 			(vreinterpretq_u16_s16): Likewise.
> 			(vreinterpretq_u16_s32): Likewise.
> 			(vreinterpretq_u16_s64): Likewise.
> 			(vreinterpretq_u16_s8): Likewise.
> 			(vreinterpretq_u16_u32): Likewise.
> 			(vreinterpretq_u16_u64): Likewise.
> 			(vreinterpretq_u16_u8): Likewise.
> 			(vreinterpretq_u32_s16): Likewise.
> 			(vreinterpretq_u32_s32): Likewise.
> 			(vreinterpretq_u32_s64): Likewise.
> 			(vreinterpretq_u32_s8): Likewise.
> 			(vreinterpretq_u32_u16): Likewise.
> 			(vreinterpretq_u32_u64): Likewise.
> 			(vreinterpretq_u32_u8): Likewise.
> 			(vreinterpretq_u64_s16): Likewise.
> 			(vreinterpretq_u64_s32): Likewise.
> 			(vreinterpretq_u64_s64): Likewise.
> 			(vreinterpretq_u64_s8): Likewise.
> 			(vreinterpretq_u64_u16): Likewise.
> 			(vreinterpretq_u64_u32): Likewise.
> 			(vreinterpretq_u64_u8): Likewise.
> 			(vreinterpretq_u8_s16): Likewise.
> 			(vreinterpretq_u8_s32): Likewise.
> 			(vreinterpretq_u8_s64): Likewise.
> 			(vreinterpretq_u8_s8): Likewise.
> 			(vreinterpretq_u8_u16): Likewise.
> 			(vreinterpretq_u8_u32): Likewise.
> 			(vreinterpretq_u8_u64): Likewise.
> 			(vreinterpretq_s32_f16): Likewise.
> 			(vreinterpretq_s32_f32): Likewise.
> 			(vreinterpretq_u16_f16): Likewise.
> 			(vreinterpretq_u16_f32): Likewise.
> 			(vreinterpretq_u32_f16): Likewise.
> 			(vreinterpretq_u32_f32): Likewise.
> 			(vreinterpretq_u64_f16): Likewise.
> 			(vreinterpretq_u64_f32): Likewise.
> 			(vreinterpretq_u8_f16): Likewise.
> 			(vreinterpretq_u8_f32): Likewise.
> 			(vreinterpretq_f16_f32): Likewise.
> 			(vreinterpretq_f16_s16): Likewise.
> 			(vreinterpretq_f16_s32): Likewise.
> 			(vreinterpretq_f16_s64): Likewise.
> 			(vreinterpretq_f16_s8): Likewise.
> 			(vreinterpretq_f16_u16): Likewise.
> 			(vreinterpretq_f16_u32): Likewise.
> 			(vreinterpretq_f16_u64): Likewise.
> 			(vreinterpretq_f16_u8): Likewise.
> 			(vreinterpretq_f32_f16): Likewise.
> 			(vreinterpretq_f32_s16): Likewise.
> 			(vreinterpretq_f32_s32): Likewise.
> 			(vreinterpretq_f32_s64): Likewise.
> 			(vreinterpretq_f32_s8): Likewise.
> 			(vreinterpretq_f32_u16): Likewise.
> 			(vreinterpretq_f32_u32): Likewise.
> 			(vreinterpretq_f32_u64): Likewise.
> 			(vreinterpretq_f32_u8): Likewise.
> 			(vreinterpretq_s16_f16): Likewise.
> 			(vreinterpretq_s16_f32): Likewise.
> 			(vreinterpretq_s64_f16): Likewise.
> 			(vreinterpretq_s64_f32): Likewise.
> 			(vreinterpretq_s8_f16): Likewise.
> 			(vreinterpretq_s8_f32): Likewise.
> 			(__arm_vreinterpretq_f16): Likewise.
> 			(__arm_vreinterpretq_f32): Likewise.
> 			(__arm_vreinterpretq_s16): Likewise.
> 			(__arm_vreinterpretq_s32): Likewise.
> 			(__arm_vreinterpretq_s64): Likewise.
> 			(__arm_vreinterpretq_s8): Likewise.
> 			(__arm_vreinterpretq_u16): Likewise.
> 			(__arm_vreinterpretq_u32): Likewise.
> 			(__arm_vreinterpretq_u64): Likewise.
> 			(__arm_vreinterpretq_u8): Likewise.
> 			* config/arm/arm_mve_types.h
> (__arm_vreinterpretq_s16_s32):
> 		Remove.
> 			(__arm_vreinterpretq_s16_s64): Likewise.
> 			(__arm_vreinterpretq_s16_s8): Likewise.
> 			(__arm_vreinterpretq_s16_u16): Likewise.
> 			(__arm_vreinterpretq_s16_u32): Likewise.
> 			(__arm_vreinterpretq_s16_u64): Likewise.
> 			(__arm_vreinterpretq_s16_u8): Likewise.
> 			(__arm_vreinterpretq_s32_s16): Likewise.
> 			(__arm_vreinterpretq_s32_s64): Likewise.
> 			(__arm_vreinterpretq_s32_s8): Likewise.
> 			(__arm_vreinterpretq_s32_u16): Likewise.
> 			(__arm_vreinterpretq_s32_u32): Likewise.
> 			(__arm_vreinterpretq_s32_u64): Likewise.
> 			(__arm_vreinterpretq_s32_u8): Likewise.
> 			(__arm_vreinterpretq_s64_s16): Likewise.
> 			(__arm_vreinterpretq_s64_s32): Likewise.
> 			(__arm_vreinterpretq_s64_s8): Likewise.
> 			(__arm_vreinterpretq_s64_u16): Likewise.
> 			(__arm_vreinterpretq_s64_u32): Likewise.
> 			(__arm_vreinterpretq_s64_u64): Likewise.
> 			(__arm_vreinterpretq_s64_u8): Likewise.
> 			(__arm_vreinterpretq_s8_s16): Likewise.
> 			(__arm_vreinterpretq_s8_s32): Likewise.
> 			(__arm_vreinterpretq_s8_s64): Likewise.
> 			(__arm_vreinterpretq_s8_u16): Likewise.
> 			(__arm_vreinterpretq_s8_u32): Likewise.
> 			(__arm_vreinterpretq_s8_u64): Likewise.
> 			(__arm_vreinterpretq_s8_u8): Likewise.
> 			(__arm_vreinterpretq_u16_s16): Likewise.
> 			(__arm_vreinterpretq_u16_s32): Likewise.
> 			(__arm_vreinterpretq_u16_s64): Likewise.
> 			(__arm_vreinterpretq_u16_s8): Likewise.
> 			(__arm_vreinterpretq_u16_u32): Likewise.
> 			(__arm_vreinterpretq_u16_u64): Likewise.
> 			(__arm_vreinterpretq_u16_u8): Likewise.
> 			(__arm_vreinterpretq_u32_s16): Likewise.
> 			(__arm_vreinterpretq_u32_s32): Likewise.
> 			(__arm_vreinterpretq_u32_s64): Likewise.
> 			(__arm_vreinterpretq_u32_s8): Likewise.
> 			(__arm_vreinterpretq_u32_u16): Likewise.
> 			(__arm_vreinterpretq_u32_u64): Likewise.
> 			(__arm_vreinterpretq_u32_u8): Likewise.
> 			(__arm_vreinterpretq_u64_s16): Likewise.
> 			(__arm_vreinterpretq_u64_s32): Likewise.
> 			(__arm_vreinterpretq_u64_s64): Likewise.
> 			(__arm_vreinterpretq_u64_s8): Likewise.
> 			(__arm_vreinterpretq_u64_u16): Likewise.
> 			(__arm_vreinterpretq_u64_u32): Likewise.
> 			(__arm_vreinterpretq_u64_u8): Likewise.
> 			(__arm_vreinterpretq_u8_s16): Likewise.
> 			(__arm_vreinterpretq_u8_s32): Likewise.
> 			(__arm_vreinterpretq_u8_s64): Likewise.
> 			(__arm_vreinterpretq_u8_s8): Likewise.
> 			(__arm_vreinterpretq_u8_u16): Likewise.
> 			(__arm_vreinterpretq_u8_u32): Likewise.
> 			(__arm_vreinterpretq_u8_u64): Likewise.
> 			(__arm_vreinterpretq_s32_f16): Likewise.
> 			(__arm_vreinterpretq_s32_f32): Likewise.
> 			(__arm_vreinterpretq_s16_f16): Likewise.
> 			(__arm_vreinterpretq_s16_f32): Likewise.
> 			(__arm_vreinterpretq_s64_f16): Likewise.
> 			(__arm_vreinterpretq_s64_f32): Likewise.
> 			(__arm_vreinterpretq_s8_f16): Likewise.
> 			(__arm_vreinterpretq_s8_f32): Likewise.
> 			(__arm_vreinterpretq_u16_f16): Likewise.
> 			(__arm_vreinterpretq_u16_f32): Likewise.
> 			(__arm_vreinterpretq_u32_f16): Likewise.
> 			(__arm_vreinterpretq_u32_f32): Likewise.
> 			(__arm_vreinterpretq_u64_f16): Likewise.
> 			(__arm_vreinterpretq_u64_f32): Likewise.
> 			(__arm_vreinterpretq_u8_f16): Likewise.
> 			(__arm_vreinterpretq_u8_f32): Likewise.
> 			(__arm_vreinterpretq_f16_f32): Likewise.
> 			(__arm_vreinterpretq_f16_s16): Likewise.
> 			(__arm_vreinterpretq_f16_s32): Likewise.
> 			(__arm_vreinterpretq_f16_s64): Likewise.
> 			(__arm_vreinterpretq_f16_s8): Likewise.
> 			(__arm_vreinterpretq_f16_u16): Likewise.
> 			(__arm_vreinterpretq_f16_u32): Likewise.
> 			(__arm_vreinterpretq_f16_u64): Likewise.
> 			(__arm_vreinterpretq_f16_u8): Likewise.
> 			(__arm_vreinterpretq_f32_f16): Likewise.
> 			(__arm_vreinterpretq_f32_s16): Likewise.
> 			(__arm_vreinterpretq_f32_s32): Likewise.
> 			(__arm_vreinterpretq_f32_s64): Likewise.
> 			(__arm_vreinterpretq_f32_s8): Likewise.
> 			(__arm_vreinterpretq_f32_u16): Likewise.
> 			(__arm_vreinterpretq_f32_u32): Likewise.
> 			(__arm_vreinterpretq_f32_u64): Likewise.
> 			(__arm_vreinterpretq_f32_u8): Likewise.
> 			(__arm_vreinterpretq_s16): Likewise.
> 			(__arm_vreinterpretq_s32): Likewise.
> 			(__arm_vreinterpretq_s64): Likewise.
> 			(__arm_vreinterpretq_s8): Likewise.
> 			(__arm_vreinterpretq_u16): Likewise.
> 			(__arm_vreinterpretq_u32): Likewise.
> 			(__arm_vreinterpretq_u64): Likewise.
> 			(__arm_vreinterpretq_u8): Likewise.
> 			(__arm_vreinterpretq_f16): Likewise.
> 			(__arm_vreinterpretq_f32): Likewise.
> 			* config/arm/mve.md
> (@arm_mve_reinterpret<mode>): New
> 		pattern.
> 			* config/arm/unspecs.md: (REINTERPRET): New
> unspec.
> 
> 			gcc/testsuite/
> 			* g++.target/arm/mve.exp: Add general-c++ and
> general directories.
> 			* g++.target/arm/mve/general-c++/nomve_fp_1.c:
> New test.
> 			* g++.target/arm/mve/general-c++/vreinterpretq_1.C:
> New test.
> 			* gcc.target/arm/mve/general-c/nomve_fp_1.c: New
> test.
> 			* gcc.target/arm/mve/general-c/vreinterpretq_1.c:
> New test.
> 		---
> 		 gcc/config/arm/arm-mve-builtins-base.cc       |   29 +
> 		 gcc/config/arm/arm-mve-builtins-base.def      |    2 +
> 		 gcc/config/arm/arm-mve-builtins-base.h        |    2 +
> 		 gcc/config/arm/arm-mve-builtins-shapes.cc     |   28 +
> 		 gcc/config/arm/arm-mve-builtins-shapes.h      |    8 +
> 		 gcc/config/arm/arm-mve-builtins.cc            |   60 +
> 		 gcc/config/arm/arm_mve.h                      |  300 ----
> 		 gcc/config/arm/arm_mve_types.h                | 1365 +-------------
> ---
> 		 gcc/config/arm/mve.md                         |   18 +
> 		 gcc/config/arm/unspecs.md                     |    1 +
> 		 gcc/testsuite/g++.target/arm/mve.exp          |    8 +-
> 		 .../arm/mve/general-c++/nomve_fp_1.c          |   15 +
> 		 .../arm/mve/general-c++/vreinterpretq_1.C     |   25 +
> 		 .../gcc.target/arm/mve/general-c/nomve_fp_1.c |   15 +
> 		 .../arm/mve/general-c/vreinterpretq_1.c       |   25 +
> 		 15 files changed, 286 insertions(+), 1615 deletions(-)
> 		 create mode 100644
> gcc/testsuite/g++.target/arm/mve/general-
> 		c++/nomve_fp_1.c
> 		 create mode 100644
> gcc/testsuite/g++.target/arm/mve/general-
> 		c++/vreinterpretq_1.C
> 		 create mode 100644
> gcc/testsuite/gcc.target/arm/mve/general-
> 		c/nomve_fp_1.c
> 		 create mode 100644
> gcc/testsuite/gcc.target/arm/mve/general-
> 		c/vreinterpretq_1.c
> 
> 		diff --git a/gcc/config/arm/arm-mve-builtins-base.cc
> b/gcc/config/arm/arm-
> 		mve-builtins-base.cc
> 		index e9f285faf2b..ad8d500afc6 100644
> 		--- a/gcc/config/arm/arm-mve-builtins-base.cc
> 		+++ b/gcc/config/arm/arm-mve-builtins-base.cc
> 		@@ -38,8 +38,37 @@ using namespace arm_mve;
> 
> 		 namespace {
> 
> 		+/* Implements vreinterpretq_* intrinsics.  */
> 		+class vreinterpretq_impl : public quiet<function_base>
> 		+{
> 		+  gimple *
> 		+  fold (gimple_folder &f) const override
> 		+  {
> 		+    /* Punt to rtl if the effect of the reinterpret on registers
> does not
> 		+       conform to GCC's endianness model.  */
> 		+    if (!targetm.can_change_mode_class (f.vector_mode (0),
> 		+					f.vector_mode (1),
> VFP_REGS))
> 		+      return NULL;
> 		+
> 
> 
> 	So we punt to an RTL pattern here if we cannot change mode class...
> 
> 	[snip]
> 
> 
> 		diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
> 		index 35eab6c94bf..ab688396f97 100644
> 		--- a/gcc/config/arm/mve.md
> 		+++ b/gcc/config/arm/mve.md
> 		@@ -10561,3 +10561,21 @@ (define_expand
> 		"vcond_mask_<mode><MVE_vpred>"
> 		     }
> 		   DONE;
> 		 })
> 		+
> 		+;; Reinterpret operand 1 in operand 0's mode, without
> changing its contents.
> 		+(define_expand "@arm_mve_reinterpret<mode>"
> 		+  [(set (match_operand:MVE_vecs 0 "register_operand")
> 		+	(unspec:MVE_vecs
> 		+	  [(match_operand 1 "arm_any_register_operand")]
> 		+	  REINTERPRET))]
> 		+  "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE
> (<MODE>mode))
> 		+    || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE
> 		(<MODE>mode))"
> 		+  {
> 		+    machine_mode src_mode = GET_MODE (operands[1]);
> 		+    if (targetm.can_change_mode_class (<MODE>mode,
> src_mode,
> 		VFP_REGS))
> 		+      {
> 		+	emit_move_insn (operands[0], gen_lowpart
> (<MODE>mode,
> 		operands[1]));
> 		+	DONE;
> 		+      }
> 		+  }
> 		+)
> 
> 
> 	... But we still check can_change_mode_class in this pattern and if it's
> not true we emit the new REINTERPRET unspec
> 	without a corresponding define_insn pattern. Won't that ICE? Would
> this case occur on big-endian targets?
> 
> 
> 
> 
> Looks like you are right. However, arm_mve.h is protected by:
> 
> #if __ARM_BIG_ENDIAN
> 
> #error "MVE intrinsics are not supported in Big-Endian mode."
> 
> 
> 
> 
> Just tried to hack my arm_mve.h to accept big-endian, and indeed we do ICE.
> 
> 
> 
> 
> In fact, this pattern and vreinterpretq_impl above are quite similar to the
> aarch64 implementation.
> 
> I tried with a sample
> 
> svint16_t foo(svint8_t value1)
> {
> return svreinterpret_s16_s8(value1);
> }
> and it seems aarch64-none-elf-gcc -march=armv8.2-a+sve -mbig-endian is OK,
> although
> aarch64_can_change_mode_class() has:
> if (BYTES_BIG_ENDIAN)
> ...
> if (from_sve_p && GET_MODE_UNIT_SIZE (from) != GET_MODE_UNIT_SIZE
> (to))
> return false;
> so it should have a similar problem? I', not sure why it doesn't ICE?

I believe that's because there's a pattern in aarch64-sve.md that converts everything into a simple set with the right modes forced in.

;; A pattern for handling type punning on big-endian targets.  We use a
;; special predicate for operand 1 to reduce the number of patterns.
(define_insn_and_split "*aarch64_sve_reinterpret<mode>"
  [(set (match_operand:SVE_ALL 0 "register_operand" "=w")
        (unspec:SVE_ALL
          [(match_operand 1 "aarch64_any_register_operand" "w")]
          UNSPEC_REINTERPRET))]
  "TARGET_SVE"
  "#"
  "&& reload_completed"
  [(set (match_dup 0) (match_dup 1))]
  {
    operands[1] = aarch64_replace_reg_mode (operands[1], <MODE>mode);
  }
)

I guess since we don't claim to support big-endian MVE for now we probably don't need to handle it, but I wonder whether we should instead
be asserting that targetm.can_change_mode_class is true in the folding code and adding a comment that it for future big-endian support it should be handled properly in the .md file as on aarch64?

Thanks,
Kyrill


> Thanks,
> Christophe
> 
> 
> 
> 	Thanks,
> 	Kyrill
> 
> 
> 		diff --git a/gcc/config/arm/unspecs.md
> b/gcc/config/arm/unspecs.md
> 		index 84384ee798d..dccda283573 100644
> 		--- a/gcc/config/arm/unspecs.md
> 		+++ b/gcc/config/arm/unspecs.md
> 		@@ -1255,4 +1255,5 @@ (define_c_enum "unspec" [
> 		   SQRSHRL_64
> 		   SQRSHRL_48
> 		   VSHLCQ_M_
> 		+  REINTERPRET
> 		 ])
> 
>
  
Christophe Lyon May 2, 2023, 3:49 p.m. UTC | #4
On 5/2/23 17:28, Kyrylo Tkachov wrote:
> 
> 
>> -----Original Message-----
>> From: Christophe Lyon <Christophe.Lyon@arm.com>
>> Sent: Tuesday, May 2, 2023 3:05 PM
>> To: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; gcc-patches@gcc.gnu.org;
>> Richard Earnshaw <Richard.Earnshaw@arm.com>; Richard Sandiford
>> <Richard.Sandiford@arm.com>
>> Subject: Re: [PATCH 03/22] arm: [MVE intrinsics] Rework vreinterpretq
>>
>>
>>
>>
>> On 5/2/23 12:26, Kyrylo Tkachov wrote:
>>
>>
>> 	Hi Christophe,
>>
>>
>> 		-----Original Message-----
>> 		From: Christophe Lyon <christophe.lyon@arm.com>
>> <mailto:christophe.lyon@arm.com>
>> 		Sent: Tuesday, April 18, 2023 2:46 PM
>> 		To: gcc-patches@gcc.gnu.org <mailto:gcc-
>> patches@gcc.gnu.org> ; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
>> <mailto:Kyrylo.Tkachov@arm.com> ;
>> 		Richard Earnshaw <Richard.Earnshaw@arm.com>
>> <mailto:Richard.Earnshaw@arm.com> ; Richard Sandiford
>> 		<Richard.Sandiford@arm.com>
>> <mailto:Richard.Sandiford@arm.com>
>> 		Cc: Christophe Lyon <Christophe.Lyon@arm.com>
>> <mailto:Christophe.Lyon@arm.com>
>> 		Subject: [PATCH 03/22] arm: [MVE intrinsics] Rework
>> vreinterpretq
>>
>> 		This patch implements vreinterpretq using the new MVE
>> intrinsics
>> 		framework.
>>
>> 		The old definitions for vreinterpretq are removed as a
>> consequence.
>>
>> 		2022-09-08  Murray Steele  <murray.steele@arm.com>
>> <mailto:murray.steele@arm.com>
>> 			    Christophe Lyon  <christophe.lyon@arm.com>
>> <mailto:christophe.lyon@arm.com>
>>
>> 			gcc/
>> 			* config/arm/arm-mve-builtins-base.cc
>> (vreinterpretq_impl): New
>> 		class.
>> 			* config/arm/arm-mve-builtins-base.def: Define
>> vreinterpretq.
>> 			* config/arm/arm-mve-builtins-base.h
>> (vreinterpretq): New
>> 		declaration.
>> 			* config/arm/arm-mve-builtins-shapes.cc
>> (parse_element_type): New
>> 		function.
>> 			(parse_type): Likewise.
>> 			(parse_signature): Likewise.
>> 			(build_one): Likewise.
>> 			(build_all): Likewise.
>> 			(overloaded_base): New struct.
>> 			(unary_convert_def): Likewise.
>> 			* config/arm/arm-mve-builtins-shapes.h
>> (unary_convert): Declare.
>> 			* config/arm/arm-mve-builtins.cc
>> (TYPES_reinterpret_signed1): New
>> 			macro.
>> 			(TYPES_reinterpret_unsigned1): Likewise.
>> 			(TYPES_reinterpret_integer): Likewise.
>> 			(TYPES_reinterpret_integer1): Likewise.
>> 			(TYPES_reinterpret_float1): Likewise.
>> 			(TYPES_reinterpret_float): Likewise.
>> 			(reinterpret_integer): New.
>> 			(reinterpret_float): New.
>> 			(handle_arm_mve_h): Register builtins.
>> 			* config/arm/arm_mve.h (vreinterpretq_s16):
>> Remove.
>> 			(vreinterpretq_s32): Likewise.
>> 			(vreinterpretq_s64): Likewise.
>> 			(vreinterpretq_s8): Likewise.
>> 			(vreinterpretq_u16): Likewise.
>> 			(vreinterpretq_u32): Likewise.
>> 			(vreinterpretq_u64): Likewise.
>> 			(vreinterpretq_u8): Likewise.
>> 			(vreinterpretq_f16): Likewise.
>> 			(vreinterpretq_f32): Likewise.
>> 			(vreinterpretq_s16_s32): Likewise.
>> 			(vreinterpretq_s16_s64): Likewise.
>> 			(vreinterpretq_s16_s8): Likewise.
>> 			(vreinterpretq_s16_u16): Likewise.
>> 			(vreinterpretq_s16_u32): Likewise.
>> 			(vreinterpretq_s16_u64): Likewise.
>> 			(vreinterpretq_s16_u8): Likewise.
>> 			(vreinterpretq_s32_s16): Likewise.
>> 			(vreinterpretq_s32_s64): Likewise.
>> 			(vreinterpretq_s32_s8): Likewise.
>> 			(vreinterpretq_s32_u16): Likewise.
>> 			(vreinterpretq_s32_u32): Likewise.
>> 			(vreinterpretq_s32_u64): Likewise.
>> 			(vreinterpretq_s32_u8): Likewise.
>> 			(vreinterpretq_s64_s16): Likewise.
>> 			(vreinterpretq_s64_s32): Likewise.
>> 			(vreinterpretq_s64_s8): Likewise.
>> 			(vreinterpretq_s64_u16): Likewise.
>> 			(vreinterpretq_s64_u32): Likewise.
>> 			(vreinterpretq_s64_u64): Likewise.
>> 			(vreinterpretq_s64_u8): Likewise.
>> 			(vreinterpretq_s8_s16): Likewise.
>> 			(vreinterpretq_s8_s32): Likewise.
>> 			(vreinterpretq_s8_s64): Likewise.
>> 			(vreinterpretq_s8_u16): Likewise.
>> 			(vreinterpretq_s8_u32): Likewise.
>> 			(vreinterpretq_s8_u64): Likewise.
>> 			(vreinterpretq_s8_u8): Likewise.
>> 			(vreinterpretq_u16_s16): Likewise.
>> 			(vreinterpretq_u16_s32): Likewise.
>> 			(vreinterpretq_u16_s64): Likewise.
>> 			(vreinterpretq_u16_s8): Likewise.
>> 			(vreinterpretq_u16_u32): Likewise.
>> 			(vreinterpretq_u16_u64): Likewise.
>> 			(vreinterpretq_u16_u8): Likewise.
>> 			(vreinterpretq_u32_s16): Likewise.
>> 			(vreinterpretq_u32_s32): Likewise.
>> 			(vreinterpretq_u32_s64): Likewise.
>> 			(vreinterpretq_u32_s8): Likewise.
>> 			(vreinterpretq_u32_u16): Likewise.
>> 			(vreinterpretq_u32_u64): Likewise.
>> 			(vreinterpretq_u32_u8): Likewise.
>> 			(vreinterpretq_u64_s16): Likewise.
>> 			(vreinterpretq_u64_s32): Likewise.
>> 			(vreinterpretq_u64_s64): Likewise.
>> 			(vreinterpretq_u64_s8): Likewise.
>> 			(vreinterpretq_u64_u16): Likewise.
>> 			(vreinterpretq_u64_u32): Likewise.
>> 			(vreinterpretq_u64_u8): Likewise.
>> 			(vreinterpretq_u8_s16): Likewise.
>> 			(vreinterpretq_u8_s32): Likewise.
>> 			(vreinterpretq_u8_s64): Likewise.
>> 			(vreinterpretq_u8_s8): Likewise.
>> 			(vreinterpretq_u8_u16): Likewise.
>> 			(vreinterpretq_u8_u32): Likewise.
>> 			(vreinterpretq_u8_u64): Likewise.
>> 			(vreinterpretq_s32_f16): Likewise.
>> 			(vreinterpretq_s32_f32): Likewise.
>> 			(vreinterpretq_u16_f16): Likewise.
>> 			(vreinterpretq_u16_f32): Likewise.
>> 			(vreinterpretq_u32_f16): Likewise.
>> 			(vreinterpretq_u32_f32): Likewise.
>> 			(vreinterpretq_u64_f16): Likewise.
>> 			(vreinterpretq_u64_f32): Likewise.
>> 			(vreinterpretq_u8_f16): Likewise.
>> 			(vreinterpretq_u8_f32): Likewise.
>> 			(vreinterpretq_f16_f32): Likewise.
>> 			(vreinterpretq_f16_s16): Likewise.
>> 			(vreinterpretq_f16_s32): Likewise.
>> 			(vreinterpretq_f16_s64): Likewise.
>> 			(vreinterpretq_f16_s8): Likewise.
>> 			(vreinterpretq_f16_u16): Likewise.
>> 			(vreinterpretq_f16_u32): Likewise.
>> 			(vreinterpretq_f16_u64): Likewise.
>> 			(vreinterpretq_f16_u8): Likewise.
>> 			(vreinterpretq_f32_f16): Likewise.
>> 			(vreinterpretq_f32_s16): Likewise.
>> 			(vreinterpretq_f32_s32): Likewise.
>> 			(vreinterpretq_f32_s64): Likewise.
>> 			(vreinterpretq_f32_s8): Likewise.
>> 			(vreinterpretq_f32_u16): Likewise.
>> 			(vreinterpretq_f32_u32): Likewise.
>> 			(vreinterpretq_f32_u64): Likewise.
>> 			(vreinterpretq_f32_u8): Likewise.
>> 			(vreinterpretq_s16_f16): Likewise.
>> 			(vreinterpretq_s16_f32): Likewise.
>> 			(vreinterpretq_s64_f16): Likewise.
>> 			(vreinterpretq_s64_f32): Likewise.
>> 			(vreinterpretq_s8_f16): Likewise.
>> 			(vreinterpretq_s8_f32): Likewise.
>> 			(__arm_vreinterpretq_f16): Likewise.
>> 			(__arm_vreinterpretq_f32): Likewise.
>> 			(__arm_vreinterpretq_s16): Likewise.
>> 			(__arm_vreinterpretq_s32): Likewise.
>> 			(__arm_vreinterpretq_s64): Likewise.
>> 			(__arm_vreinterpretq_s8): Likewise.
>> 			(__arm_vreinterpretq_u16): Likewise.
>> 			(__arm_vreinterpretq_u32): Likewise.
>> 			(__arm_vreinterpretq_u64): Likewise.
>> 			(__arm_vreinterpretq_u8): Likewise.
>> 			* config/arm/arm_mve_types.h
>> (__arm_vreinterpretq_s16_s32):
>> 		Remove.
>> 			(__arm_vreinterpretq_s16_s64): Likewise.
>> 			(__arm_vreinterpretq_s16_s8): Likewise.
>> 			(__arm_vreinterpretq_s16_u16): Likewise.
>> 			(__arm_vreinterpretq_s16_u32): Likewise.
>> 			(__arm_vreinterpretq_s16_u64): Likewise.
>> 			(__arm_vreinterpretq_s16_u8): Likewise.
>> 			(__arm_vreinterpretq_s32_s16): Likewise.
>> 			(__arm_vreinterpretq_s32_s64): Likewise.
>> 			(__arm_vreinterpretq_s32_s8): Likewise.
>> 			(__arm_vreinterpretq_s32_u16): Likewise.
>> 			(__arm_vreinterpretq_s32_u32): Likewise.
>> 			(__arm_vreinterpretq_s32_u64): Likewise.
>> 			(__arm_vreinterpretq_s32_u8): Likewise.
>> 			(__arm_vreinterpretq_s64_s16): Likewise.
>> 			(__arm_vreinterpretq_s64_s32): Likewise.
>> 			(__arm_vreinterpretq_s64_s8): Likewise.
>> 			(__arm_vreinterpretq_s64_u16): Likewise.
>> 			(__arm_vreinterpretq_s64_u32): Likewise.
>> 			(__arm_vreinterpretq_s64_u64): Likewise.
>> 			(__arm_vreinterpretq_s64_u8): Likewise.
>> 			(__arm_vreinterpretq_s8_s16): Likewise.
>> 			(__arm_vreinterpretq_s8_s32): Likewise.
>> 			(__arm_vreinterpretq_s8_s64): Likewise.
>> 			(__arm_vreinterpretq_s8_u16): Likewise.
>> 			(__arm_vreinterpretq_s8_u32): Likewise.
>> 			(__arm_vreinterpretq_s8_u64): Likewise.
>> 			(__arm_vreinterpretq_s8_u8): Likewise.
>> 			(__arm_vreinterpretq_u16_s16): Likewise.
>> 			(__arm_vreinterpretq_u16_s32): Likewise.
>> 			(__arm_vreinterpretq_u16_s64): Likewise.
>> 			(__arm_vreinterpretq_u16_s8): Likewise.
>> 			(__arm_vreinterpretq_u16_u32): Likewise.
>> 			(__arm_vreinterpretq_u16_u64): Likewise.
>> 			(__arm_vreinterpretq_u16_u8): Likewise.
>> 			(__arm_vreinterpretq_u32_s16): Likewise.
>> 			(__arm_vreinterpretq_u32_s32): Likewise.
>> 			(__arm_vreinterpretq_u32_s64): Likewise.
>> 			(__arm_vreinterpretq_u32_s8): Likewise.
>> 			(__arm_vreinterpretq_u32_u16): Likewise.
>> 			(__arm_vreinterpretq_u32_u64): Likewise.
>> 			(__arm_vreinterpretq_u32_u8): Likewise.
>> 			(__arm_vreinterpretq_u64_s16): Likewise.
>> 			(__arm_vreinterpretq_u64_s32): Likewise.
>> 			(__arm_vreinterpretq_u64_s64): Likewise.
>> 			(__arm_vreinterpretq_u64_s8): Likewise.
>> 			(__arm_vreinterpretq_u64_u16): Likewise.
>> 			(__arm_vreinterpretq_u64_u32): Likewise.
>> 			(__arm_vreinterpretq_u64_u8): Likewise.
>> 			(__arm_vreinterpretq_u8_s16): Likewise.
>> 			(__arm_vreinterpretq_u8_s32): Likewise.
>> 			(__arm_vreinterpretq_u8_s64): Likewise.
>> 			(__arm_vreinterpretq_u8_s8): Likewise.
>> 			(__arm_vreinterpretq_u8_u16): Likewise.
>> 			(__arm_vreinterpretq_u8_u32): Likewise.
>> 			(__arm_vreinterpretq_u8_u64): Likewise.
>> 			(__arm_vreinterpretq_s32_f16): Likewise.
>> 			(__arm_vreinterpretq_s32_f32): Likewise.
>> 			(__arm_vreinterpretq_s16_f16): Likewise.
>> 			(__arm_vreinterpretq_s16_f32): Likewise.
>> 			(__arm_vreinterpretq_s64_f16): Likewise.
>> 			(__arm_vreinterpretq_s64_f32): Likewise.
>> 			(__arm_vreinterpretq_s8_f16): Likewise.
>> 			(__arm_vreinterpretq_s8_f32): Likewise.
>> 			(__arm_vreinterpretq_u16_f16): Likewise.
>> 			(__arm_vreinterpretq_u16_f32): Likewise.
>> 			(__arm_vreinterpretq_u32_f16): Likewise.
>> 			(__arm_vreinterpretq_u32_f32): Likewise.
>> 			(__arm_vreinterpretq_u64_f16): Likewise.
>> 			(__arm_vreinterpretq_u64_f32): Likewise.
>> 			(__arm_vreinterpretq_u8_f16): Likewise.
>> 			(__arm_vreinterpretq_u8_f32): Likewise.
>> 			(__arm_vreinterpretq_f16_f32): Likewise.
>> 			(__arm_vreinterpretq_f16_s16): Likewise.
>> 			(__arm_vreinterpretq_f16_s32): Likewise.
>> 			(__arm_vreinterpretq_f16_s64): Likewise.
>> 			(__arm_vreinterpretq_f16_s8): Likewise.
>> 			(__arm_vreinterpretq_f16_u16): Likewise.
>> 			(__arm_vreinterpretq_f16_u32): Likewise.
>> 			(__arm_vreinterpretq_f16_u64): Likewise.
>> 			(__arm_vreinterpretq_f16_u8): Likewise.
>> 			(__arm_vreinterpretq_f32_f16): Likewise.
>> 			(__arm_vreinterpretq_f32_s16): Likewise.
>> 			(__arm_vreinterpretq_f32_s32): Likewise.
>> 			(__arm_vreinterpretq_f32_s64): Likewise.
>> 			(__arm_vreinterpretq_f32_s8): Likewise.
>> 			(__arm_vreinterpretq_f32_u16): Likewise.
>> 			(__arm_vreinterpretq_f32_u32): Likewise.
>> 			(__arm_vreinterpretq_f32_u64): Likewise.
>> 			(__arm_vreinterpretq_f32_u8): Likewise.
>> 			(__arm_vreinterpretq_s16): Likewise.
>> 			(__arm_vreinterpretq_s32): Likewise.
>> 			(__arm_vreinterpretq_s64): Likewise.
>> 			(__arm_vreinterpretq_s8): Likewise.
>> 			(__arm_vreinterpretq_u16): Likewise.
>> 			(__arm_vreinterpretq_u32): Likewise.
>> 			(__arm_vreinterpretq_u64): Likewise.
>> 			(__arm_vreinterpretq_u8): Likewise.
>> 			(__arm_vreinterpretq_f16): Likewise.
>> 			(__arm_vreinterpretq_f32): Likewise.
>> 			* config/arm/mve.md
>> (@arm_mve_reinterpret<mode>): New
>> 		pattern.
>> 			* config/arm/unspecs.md: (REINTERPRET): New
>> unspec.
>>
>> 			gcc/testsuite/
>> 			* g++.target/arm/mve.exp: Add general-c++ and
>> general directories.
>> 			* g++.target/arm/mve/general-c++/nomve_fp_1.c:
>> New test.
>> 			* g++.target/arm/mve/general-c++/vreinterpretq_1.C:
>> New test.
>> 			* gcc.target/arm/mve/general-c/nomve_fp_1.c: New
>> test.
>> 			* gcc.target/arm/mve/general-c/vreinterpretq_1.c:
>> New test.
>> 		---
>> 		 gcc/config/arm/arm-mve-builtins-base.cc       |   29 +
>> 		 gcc/config/arm/arm-mve-builtins-base.def      |    2 +
>> 		 gcc/config/arm/arm-mve-builtins-base.h        |    2 +
>> 		 gcc/config/arm/arm-mve-builtins-shapes.cc     |   28 +
>> 		 gcc/config/arm/arm-mve-builtins-shapes.h      |    8 +
>> 		 gcc/config/arm/arm-mve-builtins.cc            |   60 +
>> 		 gcc/config/arm/arm_mve.h                      |  300 ----
>> 		 gcc/config/arm/arm_mve_types.h                | 1365 +-------------
>> ---
>> 		 gcc/config/arm/mve.md                         |   18 +
>> 		 gcc/config/arm/unspecs.md                     |    1 +
>> 		 gcc/testsuite/g++.target/arm/mve.exp          |    8 +-
>> 		 .../arm/mve/general-c++/nomve_fp_1.c          |   15 +
>> 		 .../arm/mve/general-c++/vreinterpretq_1.C     |   25 +
>> 		 .../gcc.target/arm/mve/general-c/nomve_fp_1.c |   15 +
>> 		 .../arm/mve/general-c/vreinterpretq_1.c       |   25 +
>> 		 15 files changed, 286 insertions(+), 1615 deletions(-)
>> 		 create mode 100644
>> gcc/testsuite/g++.target/arm/mve/general-
>> 		c++/nomve_fp_1.c
>> 		 create mode 100644
>> gcc/testsuite/g++.target/arm/mve/general-
>> 		c++/vreinterpretq_1.C
>> 		 create mode 100644
>> gcc/testsuite/gcc.target/arm/mve/general-
>> 		c/nomve_fp_1.c
>> 		 create mode 100644
>> gcc/testsuite/gcc.target/arm/mve/general-
>> 		c/vreinterpretq_1.c
>>
>> 		diff --git a/gcc/config/arm/arm-mve-builtins-base.cc
>> b/gcc/config/arm/arm-
>> 		mve-builtins-base.cc
>> 		index e9f285faf2b..ad8d500afc6 100644
>> 		--- a/gcc/config/arm/arm-mve-builtins-base.cc
>> 		+++ b/gcc/config/arm/arm-mve-builtins-base.cc
>> 		@@ -38,8 +38,37 @@ using namespace arm_mve;
>>
>> 		 namespace {
>>
>> 		+/* Implements vreinterpretq_* intrinsics.  */
>> 		+class vreinterpretq_impl : public quiet<function_base>
>> 		+{
>> 		+  gimple *
>> 		+  fold (gimple_folder &f) const override
>> 		+  {
>> 		+    /* Punt to rtl if the effect of the reinterpret on registers
>> does not
>> 		+       conform to GCC's endianness model.  */
>> 		+    if (!targetm.can_change_mode_class (f.vector_mode (0),
>> 		+					f.vector_mode (1),
>> VFP_REGS))
>> 		+      return NULL;
>> 		+
>>
>>
>> 	So we punt to an RTL pattern here if we cannot change mode class...
>>
>> 	[snip]
>>
>>
>> 		diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
>> 		index 35eab6c94bf..ab688396f97 100644
>> 		--- a/gcc/config/arm/mve.md
>> 		+++ b/gcc/config/arm/mve.md
>> 		@@ -10561,3 +10561,21 @@ (define_expand
>> 		"vcond_mask_<mode><MVE_vpred>"
>> 		     }
>> 		   DONE;
>> 		 })
>> 		+
>> 		+;; Reinterpret operand 1 in operand 0's mode, without
>> changing its contents.
>> 		+(define_expand "@arm_mve_reinterpret<mode>"
>> 		+  [(set (match_operand:MVE_vecs 0 "register_operand")
>> 		+	(unspec:MVE_vecs
>> 		+	  [(match_operand 1 "arm_any_register_operand")]
>> 		+	  REINTERPRET))]
>> 		+  "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE
>> (<MODE>mode))
>> 		+    || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE
>> 		(<MODE>mode))"
>> 		+  {
>> 		+    machine_mode src_mode = GET_MODE (operands[1]);
>> 		+    if (targetm.can_change_mode_class (<MODE>mode,
>> src_mode,
>> 		VFP_REGS))
>> 		+      {
>> 		+	emit_move_insn (operands[0], gen_lowpart
>> (<MODE>mode,
>> 		operands[1]));
>> 		+	DONE;
>> 		+      }
>> 		+  }
>> 		+)
>>
>>
>> 	... But we still check can_change_mode_class in this pattern and if it's
>> not true we emit the new REINTERPRET unspec
>> 	without a corresponding define_insn pattern. Won't that ICE? Would
>> this case occur on big-endian targets?
>>
>>
>>
>>
>> Looks like you are right. However, arm_mve.h is protected by:
>>
>> #if __ARM_BIG_ENDIAN
>>
>> #error "MVE intrinsics are not supported in Big-Endian mode."
>>
>>
>>
>>
>> Just tried to hack my arm_mve.h to accept big-endian, and indeed we do ICE.
>>
>>
>>
>>
>> In fact, this pattern and vreinterpretq_impl above are quite similar to the
>> aarch64 implementation.
>>
>> I tried with a sample
>>
>> svint16_t foo(svint8_t value1)
>> {
>> return svreinterpret_s16_s8(value1);
>> }
>> and it seems aarch64-none-elf-gcc -march=armv8.2-a+sve -mbig-endian is OK,
>> although
>> aarch64_can_change_mode_class() has:
>> if (BYTES_BIG_ENDIAN)
>> ...
>> if (from_sve_p && GET_MODE_UNIT_SIZE (from) != GET_MODE_UNIT_SIZE
>> (to))
>> return false;
>> so it should have a similar problem? I', not sure why it doesn't ICE?
> 
> I believe that's because there's a pattern in aarch64-sve.md that converts everything into a simple set with the right modes forced in.
> 
> ;; A pattern for handling type punning on big-endian targets.  We use a
> ;; special predicate for operand 1 to reduce the number of patterns.
> (define_insn_and_split "*aarch64_sve_reinterpret<mode>"
>    [(set (match_operand:SVE_ALL 0 "register_operand" "=w")
>          (unspec:SVE_ALL
>            [(match_operand 1 "aarch64_any_register_operand" "w")]
>            UNSPEC_REINTERPRET))]
>    "TARGET_SVE"
>    "#"
>    "&& reload_completed"
>    [(set (match_dup 0) (match_dup 1))]
>    {
>      operands[1] = aarch64_replace_reg_mode (operands[1], <MODE>mode);
>    }
> )
> 
Ha, right, thanks.

> I guess since we don't claim to support big-endian MVE for now we probably don't need to handle it, but I wonder whether we should instead
> be asserting that targetm.can_change_mode_class is true in the folding code and adding a comment that it for future big-endian support it should be handled properly in the .md file as on aarch64?
> 

Sure, I can easily add an assert, will do for v2.

Thanks,

Christophe

> Thanks,
> Kyrill
> 
> 
>> Thanks,
>> Christophe
>>
>>
>>
>> 	Thanks,
>> 	Kyrill
>>
>>
>> 		diff --git a/gcc/config/arm/unspecs.md
>> b/gcc/config/arm/unspecs.md
>> 		index 84384ee798d..dccda283573 100644
>> 		--- a/gcc/config/arm/unspecs.md
>> 		+++ b/gcc/config/arm/unspecs.md
>> 		@@ -1255,4 +1255,5 @@ (define_c_enum "unspec" [
>> 		   SQRSHRL_64
>> 		   SQRSHRL_48
>> 		   VSHLCQ_M_
>> 		+  REINTERPRET
>> 		 ])
>>
>>
>
  

Patch

diff --git a/gcc/config/arm/arm-mve-builtins-base.cc b/gcc/config/arm/arm-mve-builtins-base.cc
index e9f285faf2b..ad8d500afc6 100644
--- a/gcc/config/arm/arm-mve-builtins-base.cc
+++ b/gcc/config/arm/arm-mve-builtins-base.cc
@@ -38,8 +38,37 @@  using namespace arm_mve;
 
 namespace {
 
+/* Implements vreinterpretq_* intrinsics.  */
+class vreinterpretq_impl : public quiet<function_base>
+{
+  gimple *
+  fold (gimple_folder &f) const override
+  {
+    /* Punt to rtl if the effect of the reinterpret on registers does not
+       conform to GCC's endianness model.  */
+    if (!targetm.can_change_mode_class (f.vector_mode (0),
+					f.vector_mode (1), VFP_REGS))
+      return NULL;
+
+    /* Otherwise vreinterpret corresponds directly to a VIEW_CONVERT_EXPR
+       reinterpretation.  */
+    tree rhs = build1 (VIEW_CONVERT_EXPR, TREE_TYPE (f.lhs),
+		       gimple_call_arg (f.call, 0));
+    return gimple_build_assign (f.lhs, VIEW_CONVERT_EXPR, rhs);
+  }
+
+  rtx
+  expand (function_expander &e) const override
+  {
+    machine_mode mode = e.vector_mode (0);
+    return e.use_exact_insn (code_for_arm_mve_reinterpret (mode));
+  }
+};
+
 } /* end anonymous namespace */
 
 namespace arm_mve {
 
+FUNCTION (vreinterpretq, vreinterpretq_impl,)
+
 } /* end namespace arm_mve */
diff --git a/gcc/config/arm/arm-mve-builtins-base.def b/gcc/config/arm/arm-mve-builtins-base.def
index d15ba2e23e8..5c0c1b9cee7 100644
--- a/gcc/config/arm/arm-mve-builtins-base.def
+++ b/gcc/config/arm/arm-mve-builtins-base.def
@@ -18,7 +18,9 @@ 
    <http://www.gnu.org/licenses/>.  */
 
 #define REQUIRES_FLOAT false
+DEF_MVE_FUNCTION (vreinterpretq, unary_convert, reinterpret_integer, none)
 #undef REQUIRES_FLOAT
 
 #define REQUIRES_FLOAT true
+DEF_MVE_FUNCTION (vreinterpretq, unary_convert, reinterpret_float, none)
 #undef REQUIRES_FLOAT
diff --git a/gcc/config/arm/arm-mve-builtins-base.h b/gcc/config/arm/arm-mve-builtins-base.h
index c4d7b750cd5..60e7bd24eda 100644
--- a/gcc/config/arm/arm-mve-builtins-base.h
+++ b/gcc/config/arm/arm-mve-builtins-base.h
@@ -23,6 +23,8 @@ 
 namespace arm_mve {
 namespace functions {
 
+extern const function_base *const vreinterpretq;
+
 } /* end namespace arm_mve::functions */
 } /* end namespace arm_mve */
 
diff --git a/gcc/config/arm/arm-mve-builtins-shapes.cc b/gcc/config/arm/arm-mve-builtins-shapes.cc
index f20660d8319..d0da0ffef91 100644
--- a/gcc/config/arm/arm-mve-builtins-shapes.cc
+++ b/gcc/config/arm/arm-mve-builtins-shapes.cc
@@ -338,6 +338,34 @@  struct overloaded_base : public function_shape
   }
 };
 
+/* <T0>_t foo_t0[_t1](<T1>_t)
+
+   where the target type <t0> must be specified explicitly but the source
+   type <t1> can be inferred.
+
+   Example: vreinterpretq.
+   int16x8_t [__arm_]vreinterpretq_s16[_s8](int8x16_t a)
+   int32x4_t [__arm_]vreinterpretq_s32[_s8](int8x16_t a)
+   int8x16_t [__arm_]vreinterpretq_s8[_s16](int16x8_t a)
+   int8x16_t [__arm_]vreinterpretq_s8[_s32](int32x4_t a)  */
+struct unary_convert_def : public overloaded_base<1>
+{
+  void
+  build (function_builder &b, const function_group_info &group,
+	 bool preserve_user_namespace) const override
+  {
+    b.add_overloaded_functions (group, MODE_none, preserve_user_namespace);
+    build_all (b, "v0,v1", group, MODE_none, preserve_user_namespace);
+  }
+
+  tree
+  resolve (function_resolver &r) const override
+  {
+    return r.resolve_unary ();
+  }
+};
+SHAPE (unary_convert)
+
 } /* end namespace arm_mve */
 
 #undef SHAPE
diff --git a/gcc/config/arm/arm-mve-builtins-shapes.h b/gcc/config/arm/arm-mve-builtins-shapes.h
index 9e353b85a76..04d19a02890 100644
--- a/gcc/config/arm/arm-mve-builtins-shapes.h
+++ b/gcc/config/arm/arm-mve-builtins-shapes.h
@@ -22,8 +22,16 @@ 
 
 namespace arm_mve
 {
+  /* The naming convention is:
+
+     - to use names like "unary" etc. if the rules are somewhat generic,
+       especially if there are no ranges involved.  */
+
   namespace shapes
   {
+
+    extern const function_shape *const unary_convert;
+
   } /* end namespace arm_mve::shapes */
 } /* end namespace arm_mve */
 
diff --git a/gcc/config/arm/arm-mve-builtins.cc b/gcc/config/arm/arm-mve-builtins.cc
index b0cceb75ceb..e409a029346 100644
--- a/gcc/config/arm/arm-mve-builtins.cc
+++ b/gcc/config/arm/arm-mve-builtins.cc
@@ -199,6 +199,52 @@  CONSTEXPR const type_suffix_info type_suffixes[NUM_TYPE_SUFFIXES + 1] = {
 #define TYPES_signed_32(S, D) \
   S (s32)
 
+#define TYPES_reinterpret_signed1(D, A) \
+  D (A, s8), D (A, s16), D (A, s32), D (A, s64)
+
+#define TYPES_reinterpret_unsigned1(D, A) \
+  D (A, u8), D (A, u16), D (A, u32), D (A, u64)
+
+#define TYPES_reinterpret_integer(S, D) \
+  TYPES_reinterpret_unsigned1 (D, s8), \
+  D (s8, s16), D (s8, s32), D (s8, s64), \
+  TYPES_reinterpret_unsigned1 (D, s16), \
+  D (s16, s8), D (s16, s32), D (s16, s64), \
+  TYPES_reinterpret_unsigned1 (D, s32), \
+  D (s32, s8), D (s32, s16), D (s32, s64), \
+  TYPES_reinterpret_unsigned1 (D, s64), \
+  D (s64, s8), D (s64, s16), D (s64, s32), \
+  TYPES_reinterpret_signed1 (D, u8), \
+  D (u8, u16), D (u8, u32), D (u8, u64), \
+  TYPES_reinterpret_signed1 (D, u16), \
+  D (u16, u8), D (u16, u32), D (u16, u64), \
+  TYPES_reinterpret_signed1 (D, u32), \
+  D (u32, u8), D (u32, u16), D (u32, u64), \
+  TYPES_reinterpret_signed1 (D, u64), \
+  D (u64, u8), D (u64, u16), D (u64, u32)
+
+/* { _s8  _s16 _s32 _s64 } x { _s8  _s16 _s32 _s64 }
+   { _u8  _u16 _u32 _u64 }   { _u8  _u16 _u32 _u64 }.  */
+#define TYPES_reinterpret_integer1(D, A) \
+  TYPES_reinterpret_signed1 (D, A), \
+  TYPES_reinterpret_unsigned1 (D, A)
+
+#define TYPES_reinterpret_float1(D, A) \
+  D (A, f16), D (A, f32)
+
+#define TYPES_reinterpret_float(S, D) \
+  TYPES_reinterpret_float1 (D, s8), \
+  TYPES_reinterpret_float1 (D, s16), \
+  TYPES_reinterpret_float1 (D, s32), \
+  TYPES_reinterpret_float1 (D, s64), \
+  TYPES_reinterpret_float1 (D, u8), \
+  TYPES_reinterpret_float1 (D, u16), \
+  TYPES_reinterpret_float1 (D, u32), \
+  TYPES_reinterpret_float1 (D, u64), \
+  TYPES_reinterpret_integer1 (D, f16), \
+  TYPES_reinterpret_integer1 (D, f32), \
+  D (f16, f32), D (f32, f16)
+
 /* Describe a pair of type suffixes in which only the first is used.  */
 #define DEF_VECTOR_TYPE(X) { TYPE_SUFFIX_ ## X, NUM_TYPE_SUFFIXES }
 
@@ -231,6 +277,8 @@  DEF_MVE_TYPES_ARRAY (integer_16_32);
 DEF_MVE_TYPES_ARRAY (integer_32);
 DEF_MVE_TYPES_ARRAY (signed_16_32);
 DEF_MVE_TYPES_ARRAY (signed_32);
+DEF_MVE_TYPES_ARRAY (reinterpret_integer);
+DEF_MVE_TYPES_ARRAY (reinterpret_float);
 
 /* Used by functions that have no governing predicate.  */
 static const predication_index preds_none[] = { PRED_none, NUM_PREDS };
@@ -253,6 +301,14 @@  static const predication_index preds_p_or_none[] = {
   PRED_p, PRED_none, NUM_PREDS
 };
 
+/* A list of all MVE ACLE functions.  */
+static CONSTEXPR const function_group_info function_groups[] = {
+#define DEF_MVE_FUNCTION(NAME, SHAPE, TYPES, PREDS)			\
+  { #NAME, &functions::NAME, &shapes::SHAPE, types_##TYPES, preds_##PREDS, \
+    REQUIRES_FLOAT },
+#include "arm-mve-builtins.def"
+};
+
 /* The scalar type associated with each vector type.  */
 extern GTY(()) tree scalar_types[NUM_VECTOR_TYPES];
 tree scalar_types[NUM_VECTOR_TYPES];
@@ -431,6 +487,10 @@  handle_arm_mve_h (bool preserve_user_namespace)
 
   /* Define MVE functions.  */
   function_table = new hash_table<registered_function_hasher> (1023);
+  function_builder builder;
+  for (unsigned int i = 0; i < ARRAY_SIZE (function_groups); ++i)
+    builder.register_function_group (function_groups[i],
+				     preserve_user_namespace);
 }
 
 /* Return true if CANDIDATE is equivalent to MODEL_TYPE for overloading
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 0d2ba968fc0..7688b5a7e53 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -358,14 +358,6 @@ 
 #define vstrwq_scatter_shifted_offset_p(__base, __offset, __value, __p) __arm_vstrwq_scatter_shifted_offset_p(__base, __offset, __value, __p)
 #define vstrwq_scatter_shifted_offset(__base, __offset, __value) __arm_vstrwq_scatter_shifted_offset(__base, __offset, __value)
 #define vuninitializedq(__v) __arm_vuninitializedq(__v)
-#define vreinterpretq_s16(__a) __arm_vreinterpretq_s16(__a)
-#define vreinterpretq_s32(__a) __arm_vreinterpretq_s32(__a)
-#define vreinterpretq_s64(__a) __arm_vreinterpretq_s64(__a)
-#define vreinterpretq_s8(__a) __arm_vreinterpretq_s8(__a)
-#define vreinterpretq_u16(__a) __arm_vreinterpretq_u16(__a)
-#define vreinterpretq_u32(__a) __arm_vreinterpretq_u32(__a)
-#define vreinterpretq_u64(__a) __arm_vreinterpretq_u64(__a)
-#define vreinterpretq_u8(__a) __arm_vreinterpretq_u8(__a)
 #define vddupq_m(__inactive, __a, __imm, __p) __arm_vddupq_m(__inactive, __a, __imm, __p)
 #define vddupq_u8(__a, __imm) __arm_vddupq_u8(__a, __imm)
 #define vddupq_u32(__a, __imm) __arm_vddupq_u32(__a, __imm)
@@ -518,8 +510,6 @@ 
 #define vfmsq_m(__a, __b, __c, __p) __arm_vfmsq_m(__a, __b, __c, __p)
 #define vmaxnmq_m(__inactive, __a, __b, __p) __arm_vmaxnmq_m(__inactive, __a, __b, __p)
 #define vminnmq_m(__inactive, __a, __b, __p) __arm_vminnmq_m(__inactive, __a, __b, __p)
-#define vreinterpretq_f16(__a) __arm_vreinterpretq_f16(__a)
-#define vreinterpretq_f32(__a) __arm_vreinterpretq_f32(__a)
 #define vminnmq_x(__a, __b, __p) __arm_vminnmq_x(__a, __b, __p)
 #define vmaxnmq_x(__a, __b, __p) __arm_vmaxnmq_x(__a, __b, __p)
 #define vcmulq_x(__a, __b, __p) __arm_vcmulq_x(__a, __b, __p)
@@ -2365,96 +2355,6 @@ 
 #define vaddq_u32(__a, __b) __arm_vaddq_u32(__a, __b)
 #define vaddq_f16(__a, __b) __arm_vaddq_f16(__a, __b)
 #define vaddq_f32(__a, __b) __arm_vaddq_f32(__a, __b)
-#define vreinterpretq_s16_s32(__a) __arm_vreinterpretq_s16_s32(__a)
-#define vreinterpretq_s16_s64(__a) __arm_vreinterpretq_s16_s64(__a)
-#define vreinterpretq_s16_s8(__a) __arm_vreinterpretq_s16_s8(__a)
-#define vreinterpretq_s16_u16(__a) __arm_vreinterpretq_s16_u16(__a)
-#define vreinterpretq_s16_u32(__a) __arm_vreinterpretq_s16_u32(__a)
-#define vreinterpretq_s16_u64(__a) __arm_vreinterpretq_s16_u64(__a)
-#define vreinterpretq_s16_u8(__a) __arm_vreinterpretq_s16_u8(__a)
-#define vreinterpretq_s32_s16(__a) __arm_vreinterpretq_s32_s16(__a)
-#define vreinterpretq_s32_s64(__a) __arm_vreinterpretq_s32_s64(__a)
-#define vreinterpretq_s32_s8(__a) __arm_vreinterpretq_s32_s8(__a)
-#define vreinterpretq_s32_u16(__a) __arm_vreinterpretq_s32_u16(__a)
-#define vreinterpretq_s32_u32(__a) __arm_vreinterpretq_s32_u32(__a)
-#define vreinterpretq_s32_u64(__a) __arm_vreinterpretq_s32_u64(__a)
-#define vreinterpretq_s32_u8(__a) __arm_vreinterpretq_s32_u8(__a)
-#define vreinterpretq_s64_s16(__a) __arm_vreinterpretq_s64_s16(__a)
-#define vreinterpretq_s64_s32(__a) __arm_vreinterpretq_s64_s32(__a)
-#define vreinterpretq_s64_s8(__a) __arm_vreinterpretq_s64_s8(__a)
-#define vreinterpretq_s64_u16(__a) __arm_vreinterpretq_s64_u16(__a)
-#define vreinterpretq_s64_u32(__a) __arm_vreinterpretq_s64_u32(__a)
-#define vreinterpretq_s64_u64(__a) __arm_vreinterpretq_s64_u64(__a)
-#define vreinterpretq_s64_u8(__a) __arm_vreinterpretq_s64_u8(__a)
-#define vreinterpretq_s8_s16(__a) __arm_vreinterpretq_s8_s16(__a)
-#define vreinterpretq_s8_s32(__a) __arm_vreinterpretq_s8_s32(__a)
-#define vreinterpretq_s8_s64(__a) __arm_vreinterpretq_s8_s64(__a)
-#define vreinterpretq_s8_u16(__a) __arm_vreinterpretq_s8_u16(__a)
-#define vreinterpretq_s8_u32(__a) __arm_vreinterpretq_s8_u32(__a)
-#define vreinterpretq_s8_u64(__a) __arm_vreinterpretq_s8_u64(__a)
-#define vreinterpretq_s8_u8(__a) __arm_vreinterpretq_s8_u8(__a)
-#define vreinterpretq_u16_s16(__a) __arm_vreinterpretq_u16_s16(__a)
-#define vreinterpretq_u16_s32(__a) __arm_vreinterpretq_u16_s32(__a)
-#define vreinterpretq_u16_s64(__a) __arm_vreinterpretq_u16_s64(__a)
-#define vreinterpretq_u16_s8(__a) __arm_vreinterpretq_u16_s8(__a)
-#define vreinterpretq_u16_u32(__a) __arm_vreinterpretq_u16_u32(__a)
-#define vreinterpretq_u16_u64(__a) __arm_vreinterpretq_u16_u64(__a)
-#define vreinterpretq_u16_u8(__a) __arm_vreinterpretq_u16_u8(__a)
-#define vreinterpretq_u32_s16(__a) __arm_vreinterpretq_u32_s16(__a)
-#define vreinterpretq_u32_s32(__a) __arm_vreinterpretq_u32_s32(__a)
-#define vreinterpretq_u32_s64(__a) __arm_vreinterpretq_u32_s64(__a)
-#define vreinterpretq_u32_s8(__a) __arm_vreinterpretq_u32_s8(__a)
-#define vreinterpretq_u32_u16(__a) __arm_vreinterpretq_u32_u16(__a)
-#define vreinterpretq_u32_u64(__a) __arm_vreinterpretq_u32_u64(__a)
-#define vreinterpretq_u32_u8(__a) __arm_vreinterpretq_u32_u8(__a)
-#define vreinterpretq_u64_s16(__a) __arm_vreinterpretq_u64_s16(__a)
-#define vreinterpretq_u64_s32(__a) __arm_vreinterpretq_u64_s32(__a)
-#define vreinterpretq_u64_s64(__a) __arm_vreinterpretq_u64_s64(__a)
-#define vreinterpretq_u64_s8(__a) __arm_vreinterpretq_u64_s8(__a)
-#define vreinterpretq_u64_u16(__a) __arm_vreinterpretq_u64_u16(__a)
-#define vreinterpretq_u64_u32(__a) __arm_vreinterpretq_u64_u32(__a)
-#define vreinterpretq_u64_u8(__a) __arm_vreinterpretq_u64_u8(__a)
-#define vreinterpretq_u8_s16(__a) __arm_vreinterpretq_u8_s16(__a)
-#define vreinterpretq_u8_s32(__a) __arm_vreinterpretq_u8_s32(__a)
-#define vreinterpretq_u8_s64(__a) __arm_vreinterpretq_u8_s64(__a)
-#define vreinterpretq_u8_s8(__a) __arm_vreinterpretq_u8_s8(__a)
-#define vreinterpretq_u8_u16(__a) __arm_vreinterpretq_u8_u16(__a)
-#define vreinterpretq_u8_u32(__a) __arm_vreinterpretq_u8_u32(__a)
-#define vreinterpretq_u8_u64(__a) __arm_vreinterpretq_u8_u64(__a)
-#define vreinterpretq_s32_f16(__a) __arm_vreinterpretq_s32_f16(__a)
-#define vreinterpretq_s32_f32(__a) __arm_vreinterpretq_s32_f32(__a)
-#define vreinterpretq_u16_f16(__a) __arm_vreinterpretq_u16_f16(__a)
-#define vreinterpretq_u16_f32(__a) __arm_vreinterpretq_u16_f32(__a)
-#define vreinterpretq_u32_f16(__a) __arm_vreinterpretq_u32_f16(__a)
-#define vreinterpretq_u32_f32(__a) __arm_vreinterpretq_u32_f32(__a)
-#define vreinterpretq_u64_f16(__a) __arm_vreinterpretq_u64_f16(__a)
-#define vreinterpretq_u64_f32(__a) __arm_vreinterpretq_u64_f32(__a)
-#define vreinterpretq_u8_f16(__a) __arm_vreinterpretq_u8_f16(__a)
-#define vreinterpretq_u8_f32(__a) __arm_vreinterpretq_u8_f32(__a)
-#define vreinterpretq_f16_f32(__a) __arm_vreinterpretq_f16_f32(__a)
-#define vreinterpretq_f16_s16(__a) __arm_vreinterpretq_f16_s16(__a)
-#define vreinterpretq_f16_s32(__a) __arm_vreinterpretq_f16_s32(__a)
-#define vreinterpretq_f16_s64(__a) __arm_vreinterpretq_f16_s64(__a)
-#define vreinterpretq_f16_s8(__a) __arm_vreinterpretq_f16_s8(__a)
-#define vreinterpretq_f16_u16(__a) __arm_vreinterpretq_f16_u16(__a)
-#define vreinterpretq_f16_u32(__a) __arm_vreinterpretq_f16_u32(__a)
-#define vreinterpretq_f16_u64(__a) __arm_vreinterpretq_f16_u64(__a)
-#define vreinterpretq_f16_u8(__a) __arm_vreinterpretq_f16_u8(__a)
-#define vreinterpretq_f32_f16(__a) __arm_vreinterpretq_f32_f16(__a)
-#define vreinterpretq_f32_s16(__a) __arm_vreinterpretq_f32_s16(__a)
-#define vreinterpretq_f32_s32(__a) __arm_vreinterpretq_f32_s32(__a)
-#define vreinterpretq_f32_s64(__a) __arm_vreinterpretq_f32_s64(__a)
-#define vreinterpretq_f32_s8(__a) __arm_vreinterpretq_f32_s8(__a)
-#define vreinterpretq_f32_u16(__a) __arm_vreinterpretq_f32_u16(__a)
-#define vreinterpretq_f32_u32(__a) __arm_vreinterpretq_f32_u32(__a)
-#define vreinterpretq_f32_u64(__a) __arm_vreinterpretq_f32_u64(__a)
-#define vreinterpretq_f32_u8(__a) __arm_vreinterpretq_f32_u8(__a)
-#define vreinterpretq_s16_f16(__a) __arm_vreinterpretq_s16_f16(__a)
-#define vreinterpretq_s16_f32(__a) __arm_vreinterpretq_s16_f32(__a)
-#define vreinterpretq_s64_f16(__a) __arm_vreinterpretq_s64_f16(__a)
-#define vreinterpretq_s64_f32(__a) __arm_vreinterpretq_s64_f32(__a)
-#define vreinterpretq_s8_f16(__a) __arm_vreinterpretq_s8_f16(__a)
-#define vreinterpretq_s8_f32(__a) __arm_vreinterpretq_s8_f32(__a)
 #define vuninitializedq_u8(void) __arm_vuninitializedq_u8(void)
 #define vuninitializedq_u16(void) __arm_vuninitializedq_u16(void)
 #define vuninitializedq_u32(void) __arm_vuninitializedq_u32(void)
@@ -37874,126 +37774,6 @@  extern void *__ARM_undef;
   int (*)[__ARM_mve_type_float16x8_t]: __arm_vuninitializedq_f16 (), \
   int (*)[__ARM_mve_type_float32x4_t]: __arm_vuninitializedq_f32 ());})
 
-#define __arm_vreinterpretq_f16(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_f16_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \
-  int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_f16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
-  int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_f16_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \
-  int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_f16_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_f16_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_f16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_f16_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_f16_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \
-  int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_f16_f32 (__ARM_mve_coerce(__p0, float32x4_t)));})
-
-#define __arm_vreinterpretq_f32(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_f32_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \
-  int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_f32_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
-  int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_f32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \
-  int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_f32_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_f32_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_f32_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_f32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_f32_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \
-  int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));})
-
-#define __arm_vreinterpretq_s16(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_s16_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \
-  int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s16_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s16_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \
-  int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s16_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s16_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s16_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s16_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \
-  int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_s16_f32 (__ARM_mve_coerce(__p0, float32x4_t)));})
-
-#define __arm_vreinterpretq_s32(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_s32_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s32_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
-  int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s32_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \
-  int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s32_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s32_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s32_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s32_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \
-  int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_s32_f32 (__ARM_mve_coerce(__p0, float32x4_t)));})
-
-#define __arm_vreinterpretq_s64(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_s64_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s64_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
-  int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s64_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s64_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s64_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s64_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s64_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s64_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \
-  int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_s64_f32 (__ARM_mve_coerce(__p0, float32x4_t)));})
-
-#define __arm_vreinterpretq_s8(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_s8_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s8_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
-  int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s8_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \
-  int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s8_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s8_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s8_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s8_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s8_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \
-  int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_s8_f32 (__ARM_mve_coerce(__p0, float32x4_t)));})
-
-#define __arm_vreinterpretq_u16(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_u16_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \
-  int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u16_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u16_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \
-  int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u16_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u16_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u16_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u16_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \
-  int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_u16_f32 (__ARM_mve_coerce(__p0, float32x4_t)));})
-
-#define __arm_vreinterpretq_u32(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_u32_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u32_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
-  int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u32_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \
-  int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u32_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u32_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u32_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u32_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \
-  int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_u32_f32 (__ARM_mve_coerce(__p0, float32x4_t)));})
-
-#define __arm_vreinterpretq_u64(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_u64_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u64_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
-  int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u64_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u64_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u64_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u64_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u64_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
-  int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u64_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \
-  int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_u64_f32 (__ARM_mve_coerce(__p0, float32x4_t)));})
-
-#define __arm_vreinterpretq_u8(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_float16x8_t]: __arm_vreinterpretq_u8_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \
-  int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u8_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
-  int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u8_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \
-  int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u8_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \
-  int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u8_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u8_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u8_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u8_u64 (__ARM_mve_coerce(__p0, uint64x2_t)), \
-  int (*)[__ARM_mve_type_float32x4_t]: __arm_vreinterpretq_u8_f32 (__ARM_mve_coerce(__p0, float32x4_t)));})
-
 #define __arm_vstrwq_scatter_base_wb(p0,p1,p2) ({ __typeof(p2) __p2 = (p2); \
   _Generic( (int (*)[__ARM_mve_typeid(__p2)])0, \
   int (*)[__ARM_mve_type_int32x4_t]: __arm_vstrwq_scatter_base_wb_s32 (p0, p1, __ARM_mve_coerce(__p2, int32x4_t)), \
@@ -39931,86 +39711,6 @@  extern void *__ARM_undef;
   int (*)[__ARM_mve_type_uint32x4_t]: __arm_vuninitializedq_u32 (), \
   int (*)[__ARM_mve_type_uint64x2_t]: __arm_vuninitializedq_u64 ());})
 
-#define __arm_vreinterpretq_s16(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s16_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s16_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \
-  int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s16_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s16_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s16_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s16_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s16_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));})
-
-#define __arm_vreinterpretq_s32(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s32_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
-  int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s32_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \
-  int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s32_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s32_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s32_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s32_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s32_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));})
-
-#define __arm_vreinterpretq_s64(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s64_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
-  int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s64_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_s64_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s64_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s64_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s64_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s64_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));})
-
-#define __arm_vreinterpretq_s8(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_s8_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
-  int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_s8_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \
-  int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_s8_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_s8_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_s8_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_s8_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_s8_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));})
-
-#define __arm_vreinterpretq_u16(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u16_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \
-  int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u16_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \
-  int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u16_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u16_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \
-  int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u16_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u16_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u16_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));})
-
-#define __arm_vreinterpretq_u32(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u32_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
-  int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u32_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \
-  int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u32_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u32_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u32_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \
-  int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u32_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \
-  int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u32_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));})
-
-#define __arm_vreinterpretq_u64(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u64_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
-  int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u64_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \
-  int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u64_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \
-  int (*)[__ARM_mve_type_uint8x16_t]: __arm_vreinterpretq_u64_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u64_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u64_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
-  int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u64_s64 (__ARM_mve_coerce(__p0, int64x2_t)));})
-
-#define __arm_vreinterpretq_u8(p0) ({ __typeof(p0) __p0 = (p0); \
-  _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \
-  int (*)[__ARM_mve_type_int16x8_t]: __arm_vreinterpretq_u8_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \
-  int (*)[__ARM_mve_type_int32x4_t]: __arm_vreinterpretq_u8_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \
-  int (*)[__ARM_mve_type_int64x2_t]: __arm_vreinterpretq_u8_s64 (__ARM_mve_coerce(__p0, int64x2_t)), \
-  int (*)[__ARM_mve_type_int8x16_t]: __arm_vreinterpretq_u8_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \
-  int (*)[__ARM_mve_type_uint16x8_t]: __arm_vreinterpretq_u8_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \
-  int (*)[__ARM_mve_type_uint32x4_t]: __arm_vreinterpretq_u8_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \
-  int (*)[__ARM_mve_type_uint64x2_t]: __arm_vreinterpretq_u8_u64 (__ARM_mve_coerce(__p0, uint64x2_t)));})
-
 #define __arm_vabsq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \
   _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \
   int (*)[__ARM_mve_type_int8x16_t]: __arm_vabsq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), p2), \
diff --git a/gcc/config/arm/arm_mve_types.h b/gcc/config/arm/arm_mve_types.h
index 12bb519142f..ae2591faa03 100644
--- a/gcc/config/arm/arm_mve_types.h
+++ b/gcc/config/arm/arm_mve_types.h
@@ -29,1124 +29,101 @@  typedef float float32_t;
 
 #pragma GCC arm "arm_mve_types.h"
 
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16_s32 (int32x4_t __a)
-{
-  return (int16x8_t)  __a;
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16_s64 (int64x2_t __a)
-{
-  return (int16x8_t)  __a;
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16_s8 (int8x16_t __a)
-{
-  return (int16x8_t)  __a;
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16_u16 (uint16x8_t __a)
-{
-  return (int16x8_t)  __a;
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16_u32 (uint32x4_t __a)
-{
-  return (int16x8_t)  __a;
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16_u64 (uint64x2_t __a)
-{
-  return (int16x8_t)  __a;
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16_u8 (uint8x16_t __a)
-{
-  return (int16x8_t)  __a;
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s32_s16 (int16x8_t __a)
-{
-  return (int32x4_t)  __a;
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s32_s64 (int64x2_t __a)
-{
-  return (int32x4_t)  __a;
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s32_s8 (int8x16_t __a)
-{
-  return (int32x4_t)  __a;
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s32_u16 (uint16x8_t __a)
-{
-  return (int32x4_t)  __a;
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s32_u32 (uint32x4_t __a)
-{
-  return (int32x4_t)  __a;
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s32_u64 (uint64x2_t __a)
-{
-  return (int32x4_t)  __a;
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s32_u8 (uint8x16_t __a)
-{
-  return (int32x4_t)  __a;
-}
-
-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64_s16 (int16x8_t __a)
-{
-  return (int64x2_t)  __a;
-}
-
-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64_s32 (int32x4_t __a)
-{
-  return (int64x2_t)  __a;
-}
-
-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64_s8 (int8x16_t __a)
-{
-  return (int64x2_t)  __a;
-}
-
-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64_u16 (uint16x8_t __a)
-{
-  return (int64x2_t)  __a;
-}
-
-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64_u32 (uint32x4_t __a)
-{
-  return (int64x2_t)  __a;
-}
-
-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64_u64 (uint64x2_t __a)
-{
-  return (int64x2_t)  __a;
-}
-
-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64_u8 (uint8x16_t __a)
-{
-  return (int64x2_t)  __a;
-}
-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s8_s16 (int16x8_t __a)
-{
-  return (int8x16_t)  __a;
-}
-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s8_s32 (int32x4_t __a)
-{
-  return (int8x16_t)  __a;
-}
-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s8_s64 (int64x2_t __a)
-{
-  return (int8x16_t)  __a;
-}
-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s8_u16 (uint16x8_t __a)
-{
-  return (int8x16_t)  __a;
-}
-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s8_u32 (uint32x4_t __a)
-{
-  return (int8x16_t)  __a;
-}
-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s8_u64 (uint64x2_t __a)
-{
-  return (int8x16_t)  __a;
-}
-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s8_u8 (uint8x16_t __a)
-{
-  return (int8x16_t)  __a;
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16_s16 (int16x8_t __a)
-{
-  return (uint16x8_t)  __a;
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16_s32 (int32x4_t __a)
-{
-  return (uint16x8_t)  __a;
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16_s64 (int64x2_t __a)
-{
-  return (uint16x8_t)  __a;
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16_s8 (int8x16_t __a)
-{
-  return (uint16x8_t)  __a;
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16_u32 (uint32x4_t __a)
-{
-  return (uint16x8_t)  __a;
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16_u64 (uint64x2_t __a)
-{
-  return (uint16x8_t)  __a;
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16_u8 (uint8x16_t __a)
-{
-  return (uint16x8_t)  __a;
-}
-
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32_s16 (int16x8_t __a)
-{
-  return (uint32x4_t)  __a;
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32_s32 (int32x4_t __a)
-{
-  return (uint32x4_t)  __a;
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32_s64 (int64x2_t __a)
-{
-  return (uint32x4_t)  __a;
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32_s8 (int8x16_t __a)
-{
-  return (uint32x4_t)  __a;
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32_u16 (uint16x8_t __a)
-{
-  return (uint32x4_t)  __a;
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32_u64 (uint64x2_t __a)
-{
-  return (uint32x4_t)  __a;
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32_u8 (uint8x16_t __a)
-{
-  return (uint32x4_t)  __a;
-}
-
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64_s16 (int16x8_t __a)
-{
-  return (uint64x2_t)  __a;
-}
-
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64_s32 (int32x4_t __a)
-{
-  return (uint64x2_t)  __a;
-}
-
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64_s64 (int64x2_t __a)
-{
-  return (uint64x2_t)  __a;
-}
-
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64_s8 (int8x16_t __a)
-{
-  return (uint64x2_t)  __a;
-}
-
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64_u16 (uint16x8_t __a)
-{
-  return (uint64x2_t)  __a;
-}
-
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64_u32 (uint32x4_t __a)
-{
-  return (uint64x2_t)  __a;
-}
-
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64_u8 (uint8x16_t __a)
-{
-  return (uint64x2_t)  __a;
-}
-
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8_s16 (int16x8_t __a)
-{
-  return (uint8x16_t)  __a;
-}
-
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8_s32 (int32x4_t __a)
-{
-  return (uint8x16_t)  __a;
-}
-
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8_s64 (int64x2_t __a)
-{
-  return (uint8x16_t)  __a;
-}
-
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8_s8 (int8x16_t __a)
-{
-  return (uint8x16_t)  __a;
-}
-
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8_u16 (uint16x8_t __a)
-{
-  return (uint8x16_t)  __a;
-}
-
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8_u32 (uint32x4_t __a)
-{
-  return (uint8x16_t)  __a;
-}
-
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8_u64 (uint64x2_t __a)
-{
-  return (uint8x16_t)  __a;
-}
-
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_u8 (void)
-{
-  uint8x16_t __uninit;
-  __asm__ ("": "=w"(__uninit));
-  return __uninit;
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_u16 (void)
-{
-  uint16x8_t __uninit;
-  __asm__ ("": "=w"(__uninit));
-  return __uninit;
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_u32 (void)
-{
-  uint32x4_t __uninit;
-  __asm__ ("": "=w"(__uninit));
-  return __uninit;
-}
-
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_u64 (void)
-{
-  uint64x2_t __uninit;
-  __asm__ ("": "=w"(__uninit));
-  return __uninit;
-}
-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_s8 (void)
-{
-  int8x16_t __uninit;
-  __asm__ ("": "=w"(__uninit));
-  return __uninit;
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_s16 (void)
-{
-  int16x8_t __uninit;
-  __asm__ ("": "=w"(__uninit));
-  return __uninit;
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_s32 (void)
-{
-  int32x4_t __uninit;
-  __asm__ ("": "=w"(__uninit));
-  return __uninit;
-}
-
-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_s64 (void)
-{
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-{
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-{
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-{
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-{
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-{
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-{
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-{
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-{
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-{
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-__arm_vreinterpretq_u64_f16 (float16x8_t __a)
-{
-  return (uint64x2_t)  __a;
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-__arm_vreinterpretq_u64_f32 (float32x4_t __a)
-{
-  return (uint64x2_t)  __a;
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-__arm_vreinterpretq_u8_f16 (float16x8_t __a)
-{
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-__arm_vreinterpretq_u8_f32 (float32x4_t __a)
-{
-  return (uint8x16_t)  __a;
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16_f32 (float32x4_t __a)
-{
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16_s16 (int16x8_t __a)
-{
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16_s32 (int32x4_t __a)
-{
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16_s64 (int64x2_t __a)
-{
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-__arm_vreinterpretq_f16_s8 (int8x16_t __a)
-{
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-__arm_vreinterpretq_f16_u16 (uint16x8_t __a)
-{
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16_u32 (uint32x4_t __a)
-{
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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-{
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16_u8 (uint8x16_t __a)
-{
-  return (float16x8_t)  __a;
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-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_f16 (float16x8_t __a)
-{
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-__arm_vreinterpretq_f32_s16 (int16x8_t __a)
-{
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-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_s32 (int32x4_t __a)
-{
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-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_s64 (int64x2_t __a)
-{
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_s8 (int8x16_t __a)
-{
-  return (float32x4_t)  __a;
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-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_u16 (uint16x8_t __a)
-{
-  return (float32x4_t)  __a;
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-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_u32 (uint32x4_t __a)
-{
-  return (float32x4_t)  __a;
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-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_u64 (uint64x2_t __a)
-{
-  return (float32x4_t)  __a;
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-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32_u8 (uint8x16_t __a)
-{
-  return (float32x4_t)  __a;
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-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_f16 (void)
-{
-  float16x8_t __uninit;
-  __asm__ ("": "=w" (__uninit));
-  return __uninit;
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vuninitializedq_f32 (void)
-{
-  float32x4_t __uninit;
-  __asm__ ("": "=w" (__uninit));
-  return __uninit;
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-
-#endif
-
-#ifdef __cplusplus
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16 (int32x4_t __a)
-{
- return __arm_vreinterpretq_s16_s32 (__a);
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-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16 (int64x2_t __a)
-{
- return __arm_vreinterpretq_s16_s64 (__a);
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16 (int8x16_t __a)
-{
- return __arm_vreinterpretq_s16_s8 (__a);
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16 (uint16x8_t __a)
-{
- return __arm_vreinterpretq_s16_u16 (__a);
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-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16 (uint32x4_t __a)
-{
- return __arm_vreinterpretq_s16_u32 (__a);
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16 (uint64x2_t __a)
-{
- return __arm_vreinterpretq_s16_u64 (__a);
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-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16 (uint8x16_t __a)
-{
- return __arm_vreinterpretq_s16_u8 (__a);
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-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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-{
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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-{
- return __arm_vreinterpretq_s32_s64 (__a);
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-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s32 (int8x16_t __a)
-{
- return __arm_vreinterpretq_s32_s8 (__a);
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-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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-{
- return __arm_vreinterpretq_s32_u16 (__a);
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s32 (uint32x4_t __a)
-{
- return __arm_vreinterpretq_s32_u32 (__a);
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-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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-{
- return __arm_vreinterpretq_s32_u64 (__a);
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-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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-{
- return __arm_vreinterpretq_s32_u8 (__a);
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-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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-{
- return __arm_vreinterpretq_s64_s16 (__a);
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-
-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64 (int32x4_t __a)
-{
- return __arm_vreinterpretq_s64_s32 (__a);
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-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64 (int8x16_t __a)
-{
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64 (uint16x8_t __a)
-{
- return __arm_vreinterpretq_s64_u16 (__a);
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-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64 (uint32x4_t __a)
-{
- return __arm_vreinterpretq_s64_u32 (__a);
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64 (uint64x2_t __a)
-{
- return __arm_vreinterpretq_s64_u64 (__a);
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-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64 (uint8x16_t __a)
-{
- return __arm_vreinterpretq_s64_u8 (__a);
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-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s8 (int16x8_t __a)
-{
- return __arm_vreinterpretq_s8_s16 (__a);
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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-{
- return __arm_vreinterpretq_s8_s32 (__a);
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-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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-{
- return __arm_vreinterpretq_s8_s64 (__a);
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-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s8 (uint16x8_t __a)
-{
- return __arm_vreinterpretq_s8_u16 (__a);
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-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s8 (uint32x4_t __a)
-{
- return __arm_vreinterpretq_s8_u32 (__a);
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-
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s8 (uint64x2_t __a)
-{
- return __arm_vreinterpretq_s8_u64 (__a);
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-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s8 (uint8x16_t __a)
-{
- return __arm_vreinterpretq_s8_u8 (__a);
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-
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16 (int16x8_t __a)
-{
- return __arm_vreinterpretq_u16_s16 (__a);
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-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16 (int32x4_t __a)
-{
- return __arm_vreinterpretq_u16_s32 (__a);
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-
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16 (int64x2_t __a)
-{
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-
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16 (int8x16_t __a)
-{
- return __arm_vreinterpretq_u16_s8 (__a);
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16 (uint32x4_t __a)
-{
- return __arm_vreinterpretq_u16_u32 (__a);
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-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16 (uint64x2_t __a)
-{
- return __arm_vreinterpretq_u16_u64 (__a);
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-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16 (uint8x16_t __a)
-{
- return __arm_vreinterpretq_u16_u8 (__a);
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-
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-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32 (int16x8_t __a)
-{
- return __arm_vreinterpretq_u32_s16 (__a);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32 (int32x4_t __a)
-{
- return __arm_vreinterpretq_u32_s32 (__a);
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-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32 (int64x2_t __a)
-{
- return __arm_vreinterpretq_u32_s64 (__a);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32 (int8x16_t __a)
-{
- return __arm_vreinterpretq_u32_s8 (__a);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32 (uint16x8_t __a)
-{
- return __arm_vreinterpretq_u32_u16 (__a);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32 (uint64x2_t __a)
-{
- return __arm_vreinterpretq_u32_u64 (__a);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32 (uint8x16_t __a)
-{
- return __arm_vreinterpretq_u32_u8 (__a);
-}
-
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64 (int16x8_t __a)
-{
- return __arm_vreinterpretq_u64_s16 (__a);
-}
-
-__extension__ extern __inline uint64x2_t
+__extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64 (int32x4_t __a)
+__arm_vuninitializedq_u8 (void)
 {
- return __arm_vreinterpretq_u64_s32 (__a);
+  uint8x16_t __uninit;
+  __asm__ ("": "=w"(__uninit));
+  return __uninit;
 }
 
-__extension__ extern __inline uint64x2_t
+__extension__ extern __inline uint16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64 (int64x2_t __a)
+__arm_vuninitializedq_u16 (void)
 {
- return __arm_vreinterpretq_u64_s64 (__a);
+  uint16x8_t __uninit;
+  __asm__ ("": "=w"(__uninit));
+  return __uninit;
 }
 
-__extension__ extern __inline uint64x2_t
+__extension__ extern __inline uint32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64 (int8x16_t __a)
+__arm_vuninitializedq_u32 (void)
 {
- return __arm_vreinterpretq_u64_s8 (__a);
+  uint32x4_t __uninit;
+  __asm__ ("": "=w"(__uninit));
+  return __uninit;
 }
 
 __extension__ extern __inline uint64x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64 (uint16x8_t __a)
+__arm_vuninitializedq_u64 (void)
 {
- return __arm_vreinterpretq_u64_u16 (__a);
+  uint64x2_t __uninit;
+  __asm__ ("": "=w"(__uninit));
+  return __uninit;
 }
 
-__extension__ extern __inline uint64x2_t
+__extension__ extern __inline int8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64 (uint32x4_t __a)
+__arm_vuninitializedq_s8 (void)
 {
- return __arm_vreinterpretq_u64_u32 (__a);
+  int8x16_t __uninit;
+  __asm__ ("": "=w"(__uninit));
+  return __uninit;
 }
 
-__extension__ extern __inline uint64x2_t
+__extension__ extern __inline int16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64 (uint8x16_t __a)
+__arm_vuninitializedq_s16 (void)
 {
- return __arm_vreinterpretq_u64_u8 (__a);
+  int16x8_t __uninit;
+  __asm__ ("": "=w"(__uninit));
+  return __uninit;
 }
 
-__extension__ extern __inline uint8x16_t
+__extension__ extern __inline int32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8 (int16x8_t __a)
+__arm_vuninitializedq_s32 (void)
 {
- return __arm_vreinterpretq_u8_s16 (__a);
+  int32x4_t __uninit;
+  __asm__ ("": "=w"(__uninit));
+  return __uninit;
 }
 
-__extension__ extern __inline uint8x16_t
+__extension__ extern __inline int64x2_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8 (int32x4_t __a)
+__arm_vuninitializedq_s64 (void)
 {
- return __arm_vreinterpretq_u8_s32 (__a);
+  int64x2_t __uninit;
+  __asm__ ("": "=w"(__uninit));
+  return __uninit;
 }
 
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8 (int64x2_t __a)
-{
- return __arm_vreinterpretq_u8_s64 (__a);
-}
+#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point.  */
 
-__extension__ extern __inline uint8x16_t
+__extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8 (int8x16_t __a)
+__arm_vuninitializedq_f16 (void)
 {
- return __arm_vreinterpretq_u8_s8 (__a);
+  float16x8_t __uninit;
+  __asm__ ("": "=w" (__uninit));
+  return __uninit;
 }
 
-__extension__ extern __inline uint8x16_t
+__extension__ extern __inline float32x4_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8 (uint16x8_t __a)
+__arm_vuninitializedq_f32 (void)
 {
- return __arm_vreinterpretq_u8_u16 (__a);
+  float32x4_t __uninit;
+  __asm__ ("": "=w" (__uninit));
+  return __uninit;
 }
 
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8 (uint32x4_t __a)
-{
- return __arm_vreinterpretq_u8_u32 (__a);
-}
+#endif
 
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8 (uint64x2_t __a)
-{
- return __arm_vreinterpretq_u8_u64 (__a);
-}
+#ifdef __cplusplus
 
 __extension__ extern __inline uint8x16_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -1205,244 +182,6 @@  __arm_vuninitializedq (int64x2_t /* __v ATTRIBUTE UNUSED */)
 }
 
 #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point.  */
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s32 (float16x8_t __a)
-{
- return __arm_vreinterpretq_s32_f16 (__a);
-}
-
-__extension__ extern __inline int32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s32 (float32x4_t __a)
-{
- return __arm_vreinterpretq_s32_f32 (__a);
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16 (float16x8_t __a)
-{
- return __arm_vreinterpretq_s16_f16 (__a);
-}
-
-__extension__ extern __inline int16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s16 (float32x4_t __a)
-{
- return __arm_vreinterpretq_s16_f32 (__a);
-}
-
-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64 (float16x8_t __a)
-{
- return __arm_vreinterpretq_s64_f16 (__a);
-}
-
-__extension__ extern __inline int64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s64 (float32x4_t __a)
-{
- return __arm_vreinterpretq_s64_f32 (__a);
-}
-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s8 (float16x8_t __a)
-{
- return __arm_vreinterpretq_s8_f16 (__a);
-}
-
-__extension__ extern __inline int8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_s8 (float32x4_t __a)
-{
- return __arm_vreinterpretq_s8_f32 (__a);
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16 (float16x8_t __a)
-{
- return __arm_vreinterpretq_u16_f16 (__a);
-}
-
-__extension__ extern __inline uint16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u16 (float32x4_t __a)
-{
- return __arm_vreinterpretq_u16_f32 (__a);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32 (float16x8_t __a)
-{
- return __arm_vreinterpretq_u32_f16 (__a);
-}
-
-__extension__ extern __inline uint32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u32 (float32x4_t __a)
-{
- return __arm_vreinterpretq_u32_f32 (__a);
-}
-
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64 (float16x8_t __a)
-{
- return __arm_vreinterpretq_u64_f16 (__a);
-}
-
-__extension__ extern __inline uint64x2_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u64 (float32x4_t __a)
-{
- return __arm_vreinterpretq_u64_f32 (__a);
-}
-
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8 (float16x8_t __a)
-{
- return __arm_vreinterpretq_u8_f16 (__a);
-}
-
-__extension__ extern __inline uint8x16_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_u8 (float32x4_t __a)
-{
- return __arm_vreinterpretq_u8_f32 (__a);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16 (float32x4_t __a)
-{
- return __arm_vreinterpretq_f16_f32 (__a);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16 (int16x8_t __a)
-{
- return __arm_vreinterpretq_f16_s16 (__a);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16 (int32x4_t __a)
-{
- return __arm_vreinterpretq_f16_s32 (__a);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16 (int64x2_t __a)
-{
- return __arm_vreinterpretq_f16_s64 (__a);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16 (int8x16_t __a)
-{
- return __arm_vreinterpretq_f16_s8 (__a);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16 (uint16x8_t __a)
-{
- return __arm_vreinterpretq_f16_u16 (__a);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16 (uint32x4_t __a)
-{
- return __arm_vreinterpretq_f16_u32 (__a);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16 (uint64x2_t __a)
-{
- return __arm_vreinterpretq_f16_u64 (__a);
-}
-
-__extension__ extern __inline float16x8_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f16 (uint8x16_t __a)
-{
- return __arm_vreinterpretq_f16_u8 (__a);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32 (float16x8_t __a)
-{
- return __arm_vreinterpretq_f32_f16 (__a);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32 (int16x8_t __a)
-{
- return __arm_vreinterpretq_f32_s16 (__a);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32 (int32x4_t __a)
-{
- return __arm_vreinterpretq_f32_s32 (__a);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32 (int64x2_t __a)
-{
- return __arm_vreinterpretq_f32_s64 (__a);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32 (int8x16_t __a)
-{
- return __arm_vreinterpretq_f32_s8 (__a);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32 (uint16x8_t __a)
-{
- return __arm_vreinterpretq_f32_u16 (__a);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32 (uint32x4_t __a)
-{
- return __arm_vreinterpretq_f32_u32 (__a);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32 (uint64x2_t __a)
-{
- return __arm_vreinterpretq_f32_u64 (__a);
-}
-
-__extension__ extern __inline float32x4_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-__arm_vreinterpretq_f32 (uint8x16_t __a)
-{
- return __arm_vreinterpretq_f32_u8 (__a);
-}
-
 __extension__ extern __inline float16x8_t
 __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
 __arm_vuninitializedq (float16x8_t /* __v ATTRIBUTE UNUSED */)
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 35eab6c94bf..ab688396f97 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -10561,3 +10561,21 @@  (define_expand "vcond_mask_<mode><MVE_vpred>"
     }
   DONE;
 })
+
+;; Reinterpret operand 1 in operand 0's mode, without changing its contents.
+(define_expand "@arm_mve_reinterpret<mode>"
+  [(set (match_operand:MVE_vecs 0 "register_operand")
+	(unspec:MVE_vecs
+	  [(match_operand 1 "arm_any_register_operand")]
+	  REINTERPRET))]
+  "(TARGET_HAVE_MVE && VALID_MVE_SI_MODE (<MODE>mode))
+    || (TARGET_HAVE_MVE_FLOAT && VALID_MVE_SF_MODE (<MODE>mode))"
+  {
+    machine_mode src_mode = GET_MODE (operands[1]);
+    if (targetm.can_change_mode_class (<MODE>mode, src_mode, VFP_REGS))
+      {
+	emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1]));
+	DONE;
+      }
+  }
+)
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index 84384ee798d..dccda283573 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -1255,4 +1255,5 @@  (define_c_enum "unspec" [
   SQRSHRL_64
   SQRSHRL_48
   VSHLCQ_M_
+  REINTERPRET
 ])
diff --git a/gcc/testsuite/g++.target/arm/mve.exp b/gcc/testsuite/g++.target/arm/mve.exp
index cd824035540..f75ec20ea64 100644
--- a/gcc/testsuite/g++.target/arm/mve.exp
+++ b/gcc/testsuite/g++.target/arm/mve.exp
@@ -42,8 +42,12 @@  set dg-do-what-default "assemble"
 dg-init
 
 # Main loop.
-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/../../gcc.target/arm/mve/intrinsics/*.\[cCS\]]] \
-	"" $DEFAULT_CXXFLAGS
+set gcc_subdir [string replace $subdir 0 2 gcc]
+set files [glob -nocomplain \
+	       "$srcdir/$subdir/../../gcc.target/arm/mve/intrinsics/*.\[cCS\]" \
+	       "$srcdir/$gcc_subdir/mve/general/*.\[cCS\]" \
+	       "$srcdir/$subdir/mve/general-c++/*.\[cCS\]"]
+dg-runtest [lsort $files] "" $DEFAULT_CXXFLAGS
 
 # All done.
 set dg-do-what-default ${save-dg-do-what-default}
diff --git a/gcc/testsuite/g++.target/arm/mve/general-c++/nomve_fp_1.c b/gcc/testsuite/g++.target/arm/mve/general-c++/nomve_fp_1.c
new file mode 100644
index 00000000000..e0692ceb8c8
--- /dev/null
+++ b/gcc/testsuite/g++.target/arm/mve/general-c++/nomve_fp_1.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* Do not use dg-add-options arm_v8_1m_mve, because this might expand to "",
+   which could imply mve+fp depending on the user settings. We want to make
+   sure the '+fp' extension is not enabled.  */
+/* { dg-options "-mfpu=auto -march=armv8.1-m.main+mve" } */
+
+#include <arm_mve.h>
+
+void
+f1 (uint8x16_t v)
+{
+  vreinterpretq_f16 (v); /* { dg-error {ACLE function 'void vreinterpretq_f16\(uint8x16_t\)' requires ISA extension 'mve.fp'} } */
+  /* { dg-message {note: you can enable mve.fp by using the command-line option '-march', or by using the 'target' attribute or pragma} "" {target *-*-*} .-1 } */
+}
diff --git a/gcc/testsuite/g++.target/arm/mve/general-c++/vreinterpretq_1.C b/gcc/testsuite/g++.target/arm/mve/general-c++/vreinterpretq_1.C
new file mode 100644
index 00000000000..8b29ee58163
--- /dev/null
+++ b/gcc/testsuite/g++.target/arm/mve/general-c++/vreinterpretq_1.C
@@ -0,0 +1,25 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+
+#include <arm_mve.h>
+
+void
+f1 (int8x16_t s8, uint16x8_t u16, float32x4_t f32)
+{
+  __arm_vreinterpretq_s8 (); /* { dg-error {no matching function for call to '__arm_vreinterpretq_s8\(\)'} } */
+  __arm_vreinterpretq_s8 (s8, s8); /* { dg-error {no matching function for call to '__arm_vreinterpretq_s8\(int8x16_t\&, int8x16_t\&\)'} } */
+  __arm_vreinterpretq_s8 (0); /* { dg-error {no matching function for call to '__arm_vreinterpretq_s8\(int\)'} } */
+  __arm_vreinterpretq_s8 (s8); /* { dg-error {no matching function for call to '__arm_vreinterpretq_s8\(int8x16_t\&\)'} } */
+  __arm_vreinterpretq_s8 (u16);
+  __arm_vreinterpretq_u16 (); /* { dg-error {no matching function for call to '__arm_vreinterpretq_u16\(\)'} } */
+  __arm_vreinterpretq_u16 (u16, u16); /* { dg-error {no matching function for call to '__arm_vreinterpretq_u16\(uint16x8_t\&, uint16x8_t\&\)'} } */
+  __arm_vreinterpretq_u16 (0); /* { dg-error {no matching function for call to '__arm_vreinterpretq_u16\(int\)'} } */
+  __arm_vreinterpretq_u16 (u16); /* { dg-error {no matching function for call to '__arm_vreinterpretq_u16\(uint16x8_t\&\)'} } */
+  __arm_vreinterpretq_u16 (f32);
+  __arm_vreinterpretq_f32 (); /* { dg-error {no matching function for call to '__arm_vreinterpretq_f32\(\)'} } */
+  __arm_vreinterpretq_f32 (f32, f32); /* { dg-error {no matching function for call to '__arm_vreinterpretq_f32\(float32x4_t\&, float32x4_t\&\)'} } */
+  __arm_vreinterpretq_f32 (0); /* { dg-error {no matching function for call to '__arm_vreinterpretq_f32\(int\)'} } */
+  __arm_vreinterpretq_f32 (f32); /* { dg-error {no matching function for call to '__arm_vreinterpretq_f32\(float32x4_t\&\)'} } */
+  __arm_vreinterpretq_f32 (s8);
+}
diff --git a/gcc/testsuite/gcc.target/arm/mve/general-c/nomve_fp_1.c b/gcc/testsuite/gcc.target/arm/mve/general-c/nomve_fp_1.c
new file mode 100644
index 00000000000..21c2af16a61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/general-c/nomve_fp_1.c
@@ -0,0 +1,15 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* Do not use dg-add-options arm_v8_1m_mve, because this might expand to "",
+   which could imply mve+fp depending on the user settings. We want to make
+   sure the '+fp' extension is not enabled.  */
+/* { dg-options "-mfpu=auto -march=armv8.1-m.main+mve" } */
+
+#include <arm_mve.h>
+
+void
+foo (uint8x16_t v)
+{
+  vreinterpretq_f16 (v); /* { dg-error {ACLE function '__arm_vreinterpretq_f16_u8' requires ISA extension 'mve.fp'} } */
+  /* { dg-message {note: you can enable mve.fp by using the command-line option '-march', or by using the 'target' attribute or pragma} "" {target *-*-*} .-1 } */
+}
diff --git a/gcc/testsuite/gcc.target/arm/mve/general-c/vreinterpretq_1.c b/gcc/testsuite/gcc.target/arm/mve/general-c/vreinterpretq_1.c
new file mode 100644
index 00000000000..0297bd50198
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/general-c/vreinterpretq_1.c
@@ -0,0 +1,25 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
+/* { dg-add-options arm_v8_1m_mve_fp } */
+
+#include <arm_mve.h>
+
+void
+f1 (int8x16_t s8, uint16x8_t u16, float32x4_t f32)
+{
+  __arm_vreinterpretq_s8 (); /* { dg-error {too few arguments to function '__arm_vreinterpretq_s8'} } */
+  __arm_vreinterpretq_s8 (s8, s8); /* { dg-error {too many arguments to function '__arm_vreinterpretq_s8'} } */
+  __arm_vreinterpretq_s8 (0); /* { dg-error {passing 'int' to argument 1 of '__arm_vreinterpretq_s8', which expects an MVE vector type} } */
+  __arm_vreinterpretq_s8 (s8); /* { dg-error {'__arm_vreinterpretq_s8' has no form that takes 'int8x16_t' arguments} } */
+  __arm_vreinterpretq_s8 (u16);
+  __arm_vreinterpretq_u16 (); /* { dg-error {too few arguments to function '__arm_vreinterpretq_u16'} } */
+  __arm_vreinterpretq_u16 (u16, u16); /* { dg-error {too many arguments to function '__arm_vreinterpretq_u16'} } */
+  __arm_vreinterpretq_u16 (0); /* { dg-error {passing 'int' to argument 1 of '__arm_vreinterpretq_u16', which expects an MVE vector type} } */
+  __arm_vreinterpretq_u16 (u16); /* { dg-error {'__arm_vreinterpretq_u16' has no form that takes 'uint16x8_t' arguments} } */
+  __arm_vreinterpretq_u16 (f32);
+  __arm_vreinterpretq_f32 (); /* { dg-error {too few arguments to function '__arm_vreinterpretq_f32'} } */
+  __arm_vreinterpretq_f32 (f32, f32); /* { dg-error {too many arguments to function '__arm_vreinterpretq_f32'} } */
+  __arm_vreinterpretq_f32 (0); /* { dg-error {passing 'int' to argument 1 of '__arm_vreinterpretq_f32', which expects an MVE vector type} } */
+  __arm_vreinterpretq_f32 (f32); /* { dg-error {'__arm_vreinterpretq_f32' has no form that takes 'float32x4_t' arguments} } */
+  __arm_vreinterpretq_f32 (s8);
+}