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Date: Mon, 17 Apr 2023 14:37:01 -0400 Message-Id: <20230417183701.2249183-11-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230417183701.2249183-1-collison@rivosinc.com> References: <20230417183701.2249183-1-collison@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763450038016588242?= X-GMAIL-MSGID: =?utf-8?q?1763450038016588242?= From: Kevin Lee 2023-04-14 Kevin Lee gcc/testsuite/ChangeLog: * config/riscv/riscv.cc (riscv_autovectorize_vector_modes): Add new vector mode * gcc.target/riscv/rvv/autovec/loop-add-rv32.c: Support 8bit type * gcc.target/riscv/rvv/autovec/loop-add.c: Ditto * gcc.target/riscv/rvv/autovec/loop-and-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-and.c: Ditto * gcc.target/riscv/rvv/autovec/loop-div-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-div.c: Ditto * gcc.target/riscv/rvv/autovec/loop-max-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-max.c: Ditto * gcc.target/riscv/rvv/autovec/loop-min-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-min.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mod-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mod.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mul-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-mul.c: Ditto * gcc.target/riscv/rvv/autovec/loop-or-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-or.c: Ditto * gcc.target/riscv/rvv/autovec/loop-sub-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-sub.c: Ditto * gcc.target/riscv/rvv/autovec/loop-xor-rv32.c: Ditto * gcc.target/riscv/rvv/autovec/loop-xor.c: Ditto --- gcc/config/riscv/riscv.cc | 1 + .../gcc.target/riscv/rvv/autovec/loop-add-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c | 5 +++-- .../gcc.target/riscv/rvv/autovec/loop-and-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c | 5 +++-- .../gcc.target/riscv/rvv/autovec/loop-div-rv32.c | 8 +++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c | 8 +++++--- .../gcc.target/riscv/rvv/autovec/loop-max-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c | 7 ++++--- .../gcc.target/riscv/rvv/autovec/loop-min-rv32.c | 7 ++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c | 7 ++++--- .../gcc.target/riscv/rvv/autovec/loop-mod-rv32.c | 8 +++++--- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c | 8 +++++--- .../gcc.target/riscv/rvv/autovec/loop-mul-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c | 5 +++-- .../gcc.target/riscv/rvv/autovec/loop-sub-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c | 5 +++-- .../gcc.target/riscv/rvv/autovec/loop-xor-rv32.c | 5 +++-- gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c | 5 +++-- 21 files changed, 73 insertions(+), 48 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 9af06d926cf..a2cb83e1916 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7147,6 +7147,7 @@ riscv_autovectorize_vector_modes (vector_modes *modes, bool) modes->safe_push (VNx8QImode); modes->safe_push (VNx4QImode); modes->safe_push (VNx2QImode); + modes->safe_push (VNx1QImode); } else if (riscv_vectorization_factor == RVV_LMUL2) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c index bdc3b6892e9..76f5a3a3ff5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] + b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c index d7f992c7d27..3d1e10bf4e1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c @@ -10,8 +10,9 @@ dst[i] = a[i] + b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvadd\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c index eb1ac5b44fd..a4c7abfb0ad 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] & b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c index ff0cc2a5df7..a795e0968a9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-and.c @@ -10,8 +10,9 @@ dst[i] = a[i] & b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvand\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvand\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c index 21960f265b7..c734bb9c5f0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] / b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c index bd675b4f6f0..9f57cd91054 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-div.c @@ -10,8 +10,9 @@ dst[i] = a[i] / b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c index 751ee9ecaa3..bd825c3dfaa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] >= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c index f4dbf3f04fc..729fbe0bc76 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-max.c @@ -10,8 +10,9 @@ dst[i] = a[i] >= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmax\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmax\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c index e51cf590577..808c2879d86 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] <= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c index 304f939f6f9..c81ba64223f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-min.c @@ -10,8 +10,9 @@ dst[i] = a[i] <= b[i] ? a[i] : b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,5 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmin\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvminu\.vv} 3 } } */ +/* { dg-final { scan-assembler-times {\tvmin\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvminu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c index 7c497f6e4cc..9ce4f82b3a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] % b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c index 7508f4a50d1..46fbff22266 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mod.c @@ -10,8 +10,9 @@ dst[i] = a[i] % b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,5 +22,6 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvrem\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vv} 3 } } */ +/* int8_t and int16_t not autovec currently */ +/* { dg-final { scan-assembler-times {\tvrem\.vv} 2 } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c index fd6dcbf9c53..336af62359e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] * b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c index 9fce40890ef..12a17d0da00 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-mul.c @@ -10,8 +10,9 @@ dst[i] = a[i] * b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvmul\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvmul\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c index 305d106abd9..b272d893114 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] | b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c index 501017bc790..52243be3712 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-or.c @@ -10,8 +10,9 @@ dst[i] = a[i] | b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvor\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c index 7d0a40ec539..6fdce0f7881 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] - b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c index c8900884f83..73369745afc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c @@ -10,8 +10,9 @@ dst[i] = a[i] - b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvsub\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c index 6a9ffdb11d5..bd43e60cceb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor-rv32.c @@ -10,8 +10,9 @@ dst[i] = a[i] ^ b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c index c9d7d7f8a75..cb3adde80c9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-xor.c @@ -10,8 +10,9 @@ dst[i] = a[i] ^ b[i]; \ } -/* *int8_t not autovec currently. */ #define TEST_ALL() \ + TEST_TYPE(int8_t) \ + TEST_TYPE(uint8_t) \ TEST_TYPE(int16_t) \ TEST_TYPE(uint16_t) \ TEST_TYPE(int32_t) \ @@ -21,4 +22,4 @@ TEST_ALL() -/* { dg-final { scan-assembler-times {\tvxor\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {\tvxor\.vv} 8 } } */