From patchwork Mon Apr 17 14:50:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 84276 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6358:3046:b0:115:7a1d:dabb with SMTP id p6csp2111443rwl; Mon, 17 Apr 2023 07:51:27 -0700 (PDT) X-Google-Smtp-Source: AKy350akz2rzHW/TfFzzSBUy4v0LfAOwGBO0lyMKwEVAUrrNKahplih8MPM94wuPmmlnvly3odZQ X-Received: by 2002:a17:906:4d46:b0:94a:474a:4dd7 with SMTP id b6-20020a1709064d4600b0094a474a4dd7mr6437163ejv.60.1681743087550; Mon, 17 Apr 2023 07:51:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681743087; cv=none; d=google.com; s=arc-20160816; b=ja4Q7dMJH2iE51UFY4H2RWoGdnLTj8MHr2vLvm+ZHKsC0boC4D+GU+gWje6yd3VR10 eJXLDAQ7jNK9dKL1dzsv0X43A2tLi4ePZo+hrAH8jtvBSw8LP+NAm0z+6/TdqcOtq2Cn xBbKn7Zm8iE/iiy26PWUBFha26aAGVr5LTD2N6+R8vZrXSfByG44/iK5TN+Ybs45SCXK n7Pu1hCpMKWSnx4zp1AdDiLFQHoGwW0y+56s38/EjpXXbkto0RsrPDSCXc5lFW3TuJXN FDR0QyO4PNl4q8UKYuM8i4OPFNFRG4nep/UGySZ7YDaxNbu5FFp8y/atIxhBWIp1vTfi UXag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=Za9ucMeFAGPHHzY/LfeCvVUQhZe4YSpiwzLEa/G6SSc=; b=tSzmq4jFmZvVH6hzGZQZerJn7xjTB5KAzsVnmVdXNjpdM82c4pEmIGr1G76+Iv26BL 1EGIAibL3+4EihNmDiWb7VYbidPTppaq53nRI7Ow2CZTxfktn8ynBWJqXFBlOKV4CvlD TRdKkmWIbshmSAdNI1n0o15kvKMlmW/n9jakzo5bIkcwA7d79pN/Fs+d5A1vQe3dkjbO mUUn0VOpDZUgWwLQyAidrV25vS0nRzi89M+lt/dBBMP6CECz0HT95+wMEKbVoUGHLgmR saAKxUAXNLdm1VR71gk461kG4q9GR7C1pjJdDc0WAxRP4AGYykTVhrhCzbqiYOlMrsFB M+pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=CmVA1TL+; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id vl15-20020a17090730cf00b0094f910f628dsi1278552ejb.709.2023.04.17.07.51.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 07:51:27 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=CmVA1TL+; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5E9B0385841C for ; Mon, 17 Apr 2023 14:51:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5E9B0385841C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1681743086; bh=Za9ucMeFAGPHHzY/LfeCvVUQhZe4YSpiwzLEa/G6SSc=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=CmVA1TL+MXENjYeWuomGfBp9UfXksJ3iY4ZBvUhXKZmfVfyd2DSzAR1E7QjFnXwON kcOT3quGpvcwRjwyUqB9kbz7p5LwT33A/7AMVaA0N2Q19QXZO5bGDt37AYIWgALjb1 Frdw4YoLmrWCfyrzuhxxaoZw/ASH4WX7QXrfW7H8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by sourceware.org (Postfix) with ESMTPS id 464503858C50 for ; Mon, 17 Apr 2023 14:50:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 464503858C50 X-IronPort-AV: E=McAfee;i="6600,9927,10683"; a="344907950" X-IronPort-AV: E=Sophos;i="5.99,204,1677571200"; d="scan'208";a="344907950" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2023 07:50:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10683"; a="721141528" X-IronPort-AV: E=Sophos;i="5.99,204,1677571200"; d="scan'208";a="721141528" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga008.jf.intel.com with ESMTP; 17 Apr 2023 07:50:30 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.46.88]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 466D91006F20; Mon, 17 Apr 2023 22:50:28 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, rguenther@suse.de, pan2.li@intel.com, yanzhang.wang@intel.com, richard.sandiford@arm.com Subject: [PATCH] RISC-V: Allow Vector IOR(V1, NOT V1) optimiztion Date: Mon, 17 Apr 2023 22:50:25 +0800 Message-Id: <20230417145025.2291874-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1763435439766222061?= X-GMAIL-MSGID: =?utf-8?q?1763435439766222061?= From: Pan Li This patch add the optimization for the vector IOR(V1, NOT V1). Assume we have below sample code. vbool32_t test_shortcut_for_riscv_vmorn_case_5(vbool32_t v1, size_t vl) { return __riscv_vmorn_mm_b32(v1, v1, vl); } Before this patch: vsetvli a5,zero,e8,mf4,ta,ma vlm.v v24,0(a1) vsetvli zero,a2,e8,mf4,ta,ma vmorn.mm v24,v24,v24 vsetvli a5,zero,e8,mf4,ta,ma vsm.v v24,0(a0) ret After this patch: vsetvli zero,a2,e8,mf4,ta,ma vmset.m v24 vsetvli a5,zero,e8,mf4,ta,ma vsm.v v24,0(a0) ret Or in RTL's perspective, from: (ior:VNx2BI (reg/v:VNx2BI 137 [ v1 ]) (not:VNx2BI (reg/v:VNx2BI 137 [ v1 ]))) to: (const_vector:VNx2BI repeat [ (const_int 1 [0x1]) ]) The similar optimization like VMANDN has enabled already. There should be no difference execpt the operator when compare the VMORN and VMANDN for such kind of optimization. The patch allows the VECTOR_BOOL IOR(V1, NOT V1) simplification besides the existing SCALAR_INT mode. gcc/ChangeLog: * machmode.h (VECTOR_BOOL_MODE_P): * simplify-rtx.cc (valid_mode_for_ior_simplification_p): (simplify_context::simplify_binary_operation_1): gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/mask_insn_shortcut.c: * gcc.target/riscv/simplify_ior_optimization.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/machmode.h | 4 ++ gcc/simplify-rtx.cc | 10 +++- .../riscv/rvv/base/mask_insn_shortcut.c | 3 +- .../riscv/simplify_ior_optimization.c | 50 +++++++++++++++++++ 4 files changed, 63 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c diff --git a/gcc/machmode.h b/gcc/machmode.h index f1865c1ef42..771bae89cb7 100644 --- a/gcc/machmode.h +++ b/gcc/machmode.h @@ -134,6 +134,10 @@ extern const unsigned char mode_class[NUM_MACHINE_MODES]; || GET_MODE_CLASS (MODE) == MODE_VECTOR_ACCUM \ || GET_MODE_CLASS (MODE) == MODE_VECTOR_UACCUM) +/* Nonzero if MODE is a vector bool mode. */ +#define VECTOR_BOOL_MODE_P(MODE) \ + (GET_MODE_CLASS (MODE) == MODE_VECTOR_BOOL) \ + /* Nonzero if MODE is a scalar integral mode. */ #define SCALAR_INT_MODE_P(MODE) \ (GET_MODE_CLASS (MODE) == MODE_INT \ diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index ee75079917f..eff27b835bf 100644 --- a/gcc/simplify-rtx.cc +++ b/gcc/simplify-rtx.cc @@ -57,6 +57,12 @@ neg_poly_int_rtx (machine_mode mode, const_rtx i) return immed_wide_int_const (-wi::to_poly_wide (i, mode), mode); } +static bool +valid_mode_for_ior_simplification_p (machine_mode mode) +{ + return SCALAR_INT_MODE_P (mode) || VECTOR_BOOL_MODE_P (mode); +} + /* Test whether expression, X, is an immediate constant that represents the most significant bit of machine mode MODE. */ @@ -3332,8 +3338,8 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, if (((GET_CODE (op0) == NOT && rtx_equal_p (XEXP (op0, 0), op1)) || (GET_CODE (op1) == NOT && rtx_equal_p (XEXP (op1, 0), op0))) && ! side_effects_p (op0) - && SCALAR_INT_MODE_P (mode)) - return constm1_rtx; + && valid_mode_for_ior_simplification_p (mode)) + return CONST1_RTX (mode); /* (ior A C) is C if all bits of A that might be nonzero are on in C. */ if (CONST_INT_P (op1) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c index 83cc4a1b5a5..57d0241675a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c @@ -233,9 +233,8 @@ vbool64_t test_shortcut_for_riscv_vmxnor_case_6(vbool64_t v1, size_t vl) { /* { dg-final { scan-assembler-not {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ /* { dg-final { scan-assembler-not {vmor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ /* { dg-final { scan-assembler-not {vmnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ -/* { dg-final { scan-assembler-times {vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */ /* { dg-final { scan-assembler-not {vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */ /* { dg-final { scan-assembler-times {vmclr\.m\s+v[0-9]+} 14 } } */ -/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 7 } } */ +/* { dg-final { scan-assembler-times {vmset\.m\s+v[0-9]+} 14 } } */ /* { dg-final { scan-assembler-times {vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 14 } } */ /* { dg-final { scan-assembler-times {vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 14 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c b/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c new file mode 100644 index 00000000000..ec3bd0baf03 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/simplify_ior_optimization.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -O2" } */ + +#include + +uint8_t test_simplify_ior_scalar_case_0 (uint8_t a) +{ + return a | ~a; +} + +uint16_t test_simplify_ior_scalar_case_1 (uint16_t a) +{ + return a | ~a; +} + +uint32_t test_simplify_ior_scalar_case_2 (uint32_t a) +{ + return a | ~a; +} + +uint64_t test_simplify_ior_scalar_case_3 (uint64_t a) +{ + return a | ~a; +} + +int8_t test_simplify_ior_scalar_case_4 (int8_t a) +{ + return a | ~a; +} + +int16_t test_simplify_ior_scalar_case_5 (int16_t a) +{ + return a | ~a; +} + +int32_t test_simplify_ior_scalar_case_6 (int32_t a) +{ + return a | ~a; +} + +int64_t test_simplify_ior_scalar_case_7 (int64_t a) +{ + return a | ~a; +} + +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*-1} 6 } } */ +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*255} 1 } } */ +/* { dg-final { scan-assembler-times {li\s+a[0-9]+,\s*65536} 1 } } */ +/* { dg-final { scan-assembler-not {or\s+a[0-9]+} } } */ +/* { dg-final { scan-assembler-not {not\s+a[0-9]+} } } */