From patchwork Fri Apr 14 17:09:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick O'Neill X-Patchwork-Id: 83531 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp538336vqo; Fri, 14 Apr 2023 10:16:50 -0700 (PDT) X-Google-Smtp-Source: AKy350Z8yu5Ul7JU1FfRvd5+9TtYYu4cWRJBfH52O51xFkOH1roxyRj2FiLV6NysT5aeqa75NKpm X-Received: by 2002:a05:6402:10d4:b0:506:70c9:b870 with SMTP id p20-20020a05640210d400b0050670c9b870mr6528330edu.3.1681492610273; Fri, 14 Apr 2023 10:16:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681492610; cv=none; d=google.com; s=arc-20160816; b=yBCPcMuYFW0pGNCqvEyxBbO8//fN4DZuD4MSKkVnMFU8d4DZ02KL5qM8kiJu36O97q GQRPPyo13CYP++1V8QdRIQYFtp2/6vKD3ds9XCHmIs4oOw524x67ZFlFphmWMy2W/heX 14JM6aobEp2rrenfXXR47GV8Q4lYYxT2Lmo2mVS86gyzHvoSIcTyUSZ4bi9j/tMFEeCP mdbubyuYry5xxDMfMLpRxUlmpB1fpsXn6dbeeCeA8qg90fMwpELHOxNvw1nRGXmVfSGt gfo9Pxqz2zI5jvZ/4tGiMJFs0ePhhSzlCzY7YdHVdoBymykBysNTDfCS/c+EimOXckWQ KQsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:dmarc-filter:delivered-to; bh=qnLt+TsVHGjqe8EKHgHA1KX1+FLBSLemmcKlSKvFz2A=; b=hDcXImStzlZFRxjzhEpX2KJxuryzO7thY7zzdNJMtJLNI5SBKvjeek/bXpINBHECYA tv4sGulXb3yNWVlgaG3oJRVQb5UopJMNQfSOCMiNYZuEO4kbVPAil2aROianXdhltYa8 qdoQQVUQBx18KUXLGgCkKE6gr/g9pNhroG+s8Tgz1rgGjk9yhnRKaXzh0vutaau89eJ0 IWA8Hbgj5q925boczToZC2tZLLz/hn6xkx6T/DYNPnZPHwlFwJS8TaFzpLICRIH0qpb6 xBCS2UP0EnK2MbFO0FvCU+srVRu1i6jl0a6laa9/OYhNv1oCPI7cZ597p1XvL85Gf9lM WeUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=ChlahbTB; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id ay21-20020a056402203500b00504de2981ebsi4301534edb.14.2023.04.14.10.16.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 10:16:50 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20221208.gappssmtp.com header.s=20221208 header.b=ChlahbTB; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F23283875411 for ; Fri, 14 Apr 2023 17:13:22 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pj1-x1044.google.com (mail-pj1-x1044.google.com [IPv6:2607:f8b0:4864:20::1044]) by sourceware.org (Postfix) with ESMTPS id 7CB113857722 for ; Fri, 14 Apr 2023 17:10:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7CB113857722 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pj1-x1044.google.com with SMTP id hg12so4453319pjb.2 for ; Fri, 14 Apr 2023 10:10:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1681492253; x=1684084253; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qnLt+TsVHGjqe8EKHgHA1KX1+FLBSLemmcKlSKvFz2A=; b=ChlahbTBaLuWseaPfCWM/+3PfTsSpcwk6mfuUD8vPfdawN4YxFL6+T7lAQl/GpOxE7 uXlOQAS2APXDktlYn2d0mFD0b5TGtRKUgB5f+JtQzCk8gpUtorhXnfk1ch+3pq5o4PJc 0YUtVsd2ot5goDcYnPQ29r9mfepNDcKKW/xUVai3lFKZ0sOVqpPmcVHl1EogTk/rOgzS XbxtOEs+BaKJkBTBloJsarOLs674BUyDNthsQscErMToCA6LJVpxOcS4OKSghAwAEmyk r+SIg7S9Flz/FH6OT4vJkscZszLFZSTMffByGSIFFwdGYju80YfA0keI8J3UiJfh+JKA QAnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681492253; x=1684084253; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qnLt+TsVHGjqe8EKHgHA1KX1+FLBSLemmcKlSKvFz2A=; b=U0EnV716rSoKQMNRtrRxzwssBLlyE+ZB4Z4X4PWaW9Ifj5tb9dPeK1lKdzwVlr0OE7 Dq9l33+6BGkjGu1OaZ+WL691JWB0NZrWpKGUOO++SQOaUvA2Iqaiq/DxLWYoZh2+YVR7 SAQMLxY51NWLj6zskmx2CSjGDiQgI9Cy+BeUib5BiMNY4SrOlv9kxJ4wZROCE4vMFmPN BOTRpW78kO9IKD0DY3JhdAiTKbCWto+hAPLIH8iSxupfJzjVKPl/HUMpKkT+n1PkXoJx eBs1A25aJ0ZETqvA5YtYQXjTAhp/Q/8EMDmIKvhX9jsCY1zdBYrFRd0096/w9fmN5vyK kDLQ== X-Gm-Message-State: AAQBX9dNmqcl6imR3KYNwfTqjj6ikVSJgsr+QcO/YRluQyIfw0W7k011 A+NJTUUdDW94q9OnW1CrX+tA/vn1A4u40eflISCwQBduq3A= X-Received: by 2002:a05:6a20:cb5c:b0:d6:7b9b:f89 with SMTP id hd28-20020a056a20cb5c00b000d67b9b0f89mr5157530pzb.4.1681492253219; Fri, 14 Apr 2023 10:10:53 -0700 (PDT) Received: from patrick-ThinkPad-X1-Carbon-Gen-8.hq.rivosinc.com ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id 12-20020aa7924c000000b006258dd63a3fsm3271902pfp.56.2023.04.14.10.10.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Apr 2023 10:10:52 -0700 (PDT) From: Patrick O'Neill To: gcc-patches@gcc.gnu.org Cc: palmer@rivosinc.com, gnu-toolchain@rivosinc.com, vineetg@rivosinc.com, andrew@sifive.com, kito.cheng@sifive.com, dlustig@nvidia.com, cmuellner@gcc.gnu.org, andrea@rivosinc.com, hboehm@google.com, jeffreyalaw@gmail.com, Patrick O'Neill Subject: [PATCH v4 07/10] RISCV: Weaken compare_exchange LR/SC pairs Date: Fri, 14 Apr 2023 10:09:39 -0700 Message-Id: <20230414170942.1695672-8-patrick@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230414170942.1695672-1-patrick@rivosinc.com> References: <20230410182348.2168356-1-patrick@rivosinc.com> <20230414170942.1695672-1-patrick@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762371900223614578?= X-GMAIL-MSGID: =?utf-8?q?1763172795177765461?= Introduce the %I and %J flags for setting the .aqrl bits on LR/SC pairs as needed. Atomic compare and exchange ops provide success and failure memory models. C++17 and later place no restrictions on the relative strength of each model, so ensure we cover both by using a model that enforces the ordering of both given models. This change brings compare_exchange LR/SC ops in line with table A.6 of the ISA manual. 2023-04-14 Patrick O'Neill * riscv.cc: Add function to get the union of two memmodels in sync.md. * riscv-protos.h: Likewise. * sync.md (atomic_cas_value_strong): Remove static .aqrl bits on SC op/.rl bits on LR op and replace with optimized %I, %J flags. Signed-off-by: Patrick O'Neill --- v3 Changelog: * Consolidate tests in [PATCH v3 10/10] --- gcc/config/riscv/riscv-protos.h | 3 +++ gcc/config/riscv/riscv.cc | 44 +++++++++++++++++++++++++++++++++ gcc/config/riscv/sync.md | 9 +++++-- 3 files changed, 54 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 4611447ddde..b03edc3e8a5 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -22,6 +22,8 @@ along with GCC; see the file COPYING3. If not see #ifndef GCC_RISCV_PROTOS_H #define GCC_RISCV_PROTOS_H +#include "memmodel.h" + /* Symbol types we understand. The order of this list must match that of the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */ enum riscv_symbol_type { @@ -79,6 +81,7 @@ extern void riscv_reinit (void); extern poly_uint64 riscv_regmode_natural_size (machine_mode); extern bool riscv_v_ext_vector_mode_p (machine_mode); extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); +extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); /* Routines implemented in riscv-c.cc. */ void riscv_cpu_cpp_builtins (cpp_reader *); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 70031b83391..b3b89bf444b 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4278,6 +4278,36 @@ riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc) fputc (')', file); } +/* Return the memory model that encapuslates both given models. */ + +enum memmodel +riscv_union_memmodels (enum memmodel model1, enum memmodel model2) +{ + model1 = memmodel_base (model1); + model2 = memmodel_base (model2); + + enum memmodel weaker = model1 <= model2 ? model1: model2; + enum memmodel stronger = model1 > model2 ? model1: model2; + + switch (stronger) + { + case MEMMODEL_SEQ_CST: + case MEMMODEL_ACQ_REL: + return stronger; + case MEMMODEL_RELEASE: + if (weaker == MEMMODEL_ACQUIRE || weaker == MEMMODEL_CONSUME) + return MEMMODEL_ACQ_REL; + else + return stronger; + case MEMMODEL_ACQUIRE: + case MEMMODEL_CONSUME: + case MEMMODEL_RELAXED: + return stronger; + default: + gcc_unreachable (); + } +} + /* Return true if the .AQ suffix should be added to an AMO to implement the acquire portion of memory model MODEL. */ @@ -4331,6 +4361,8 @@ riscv_memmodel_needs_amo_release (enum memmodel model) 'R' Print the low-part relocation associated with OP. 'C' Print the integer branch condition for comparison OP. 'A' Print the atomic operation suffix for memory model OP. + 'I' Print the LR suffix for memory model OP. + 'J' Print the SC suffix for memory model OP. 'z' Print x0 if OP is zero, otherwise print OP normally. 'i' Print i if the operand is not a register. 'S' Print shift-index of single-bit mask OP. @@ -4500,6 +4532,18 @@ riscv_print_operand (FILE *file, rtx op, int letter) fputs (".rl", file); break; + case 'I': + if (model == MEMMODEL_SEQ_CST) + fputs (".aqrl", file); + else if (riscv_memmodel_needs_amo_acquire (model)) + fputs (".aq", file); + break; + + case 'J': + if (riscv_memmodel_needs_amo_release (model)) + fputs (".rl", file); + break; + case 'i': if (code != REG) fputs ("i", file); diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index fdfc56d64a1..a31b8c4f28a 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -130,10 +130,15 @@ (clobber (match_scratch:GPR 6 "=&r"))] "TARGET_ATOMIC" { + enum memmodel model_success = (enum memmodel) INTVAL(operands[4]); + enum memmodel model_failure = (enum memmodel) INTVAL(operands[5]); + /* Find the union of the two memory models so we can satisfy both success + and failure memory models. */ + operands[5] = GEN_INT(riscv_union_memmodels(model_success, model_failure)); return "1:\;" - "lr..aqrl\t%0,%1\;" + "lr.%I5\t%0,%1\;" "bne\t%0,%z2,1f\;" - "sc..rl\t%6,%z3,%1\;" + "sc.%J5\t%6,%z3,%1\;" "bnez\t%6,1b\;" "1:"; }