RISC-V: Add test cases for the RVV mask insn shortcut.

  From: Pan Li <pan2.li@intel.com>

There are sorts of shortcut codegen for the RVV mask insn. For
example.

vmxor vd, va, va => vmclr vd.

We would like to add more optimization like this but first of all
we must add the tests for the existing shortcut optimization, to
ensure we don't break existing optimization from underlying shortcut
optimization.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: New test.
---
 .../riscv/rvv/base/mask_insn_shortcut.c       | 237 ++++++++++++++++++
 1 file changed, 237 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
  

+/* { dg-final { scan-assembler-not {vmand\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmnand\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmnandn\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-times {vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-not {vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */

It's better add more assembler check
check how many vmclr.m or vmset.m should be.


juzhe.zhong@rivai.ai
 
From: pan2.li
Date: 2023-04-14 10:32
To: gcc-patches
CC: juzhe.zhong; kito.cheng; yanzhang.wang; pan2.li
Subject: [PATCH] RISC-V: Add test cases for the RVV mask insn shortcut.
From: Pan Li <pan2.li@intel.com>
 
There are sorts of shortcut codegen for the RVV mask insn. For
example.
 
vmxor vd, va, va => vmclr vd.
 
We would like to add more optimization like this but first of all
we must add the tests for the existing shortcut optimization, to
ensure we don't break existing optimization from underlying shortcut
optimization.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: New test.
---
.../riscv/rvv/base/mask_insn_shortcut.c       | 237 ++++++++++++++++++
1 file changed, 237 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
new file mode 100644
index 00000000000..8310aabaf59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
@@ -0,0 +1,237 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test_shortcut_for_riscv_vmand_case_0(vbool1_t v1, size_t vl) {
+  return __riscv_vmand_mm_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmand_case_1(vbool2_t v1, size_t vl) {
+  return __riscv_vmand_mm_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmand_case_2(vbool4_t v1, size_t vl) {
+  return __riscv_vmand_mm_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmand_case_3(vbool8_t v1, size_t vl) {
+  return __riscv_vmand_mm_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmand_case_4(vbool16_t v1, size_t vl) {
+  return __riscv_vmand_mm_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmand_case_5(vbool32_t v1, size_t vl) {
+  return __riscv_vmand_mm_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmand_case_6(vbool64_t v1, size_t vl) {
+  return __riscv_vmand_mm_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmnand_case_0(vbool1_t v1, size_t vl) {
+  return __riscv_vmnand_mm_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmnand_case_1(vbool2_t v1, size_t vl) {
+  return __riscv_vmnand_mm_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmnand_case_2(vbool4_t v1, size_t vl) {
+  return __riscv_vmnand_mm_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmnand_case_3(vbool8_t v1, size_t vl) {
+  return __riscv_vmnand_mm_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmnand_case_4(vbool16_t v1, size_t vl) {
+  return __riscv_vmnand_mm_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmnand_case_5(vbool32_t v1, size_t vl) {
+  return __riscv_vmnand_mm_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmnand_case_6(vbool64_t v1, size_t vl) {
+  return __riscv_vmnand_mm_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmandn_case_0(vbool1_t v1, size_t vl) {
+  return __riscv_vmandn_mm_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmandn_case_1(vbool2_t v1, size_t vl) {
+  return __riscv_vmandn_mm_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmandn_case_2(vbool4_t v1, size_t vl) {
+  return __riscv_vmandn_mm_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmandn_case_3(vbool8_t v1, size_t vl) {
+  return __riscv_vmandn_mm_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmandn_case_4(vbool16_t v1, size_t vl) {
+  return __riscv_vmandn_mm_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmandn_case_5(vbool32_t v1, size_t vl) {
+  return __riscv_vmandn_mm_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmandn_case_6(vbool64_t v1, size_t vl) {
+  return __riscv_vmandn_mm_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmxor_case_0(vbool1_t v1, size_t vl) {
+  return __riscv_vmxor_mm_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmxor_case_1(vbool2_t v1, size_t vl) {
+  return __riscv_vmxor_mm_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmxor_case_2(vbool4_t v1, size_t vl) {
+  return __riscv_vmxor_mm_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmxor_case_3(vbool8_t v1, size_t vl) {
+  return __riscv_vmxor_mm_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmxor_case_4(vbool16_t v1, size_t vl) {
+  return __riscv_vmxor_mm_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmxor_case_5(vbool32_t v1, size_t vl) {
+  return __riscv_vmxor_mm_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmxor_case_6(vbool64_t v1, size_t vl) {
+  return __riscv_vmxor_mm_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmor_case_0(vbool1_t v1, size_t vl) {
+  return __riscv_vmor_mm_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmor_case_1(vbool2_t v1, size_t vl) {
+  return __riscv_vmor_mm_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmor_case_2(vbool4_t v1, size_t vl) {
+  return __riscv_vmor_mm_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmor_case_3(vbool8_t v1, size_t vl) {
+  return __riscv_vmor_mm_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmor_case_4(vbool16_t v1, size_t vl) {
+  return __riscv_vmor_mm_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmor_case_5(vbool32_t v1, size_t vl) {
+  return __riscv_vmor_mm_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmor_case_6(vbool64_t v1, size_t vl) {
+  return __riscv_vmor_mm_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmnor_case_0(vbool1_t v1, size_t vl) {
+  return __riscv_vmnor_mm_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmnor_case_1(vbool2_t v1, size_t vl) {
+  return __riscv_vmnor_mm_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmnor_case_2(vbool4_t v1, size_t vl) {
+  return __riscv_vmnor_mm_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmnor_case_3(vbool8_t v1, size_t vl) {
+  return __riscv_vmnor_mm_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmnor_case_4(vbool16_t v1, size_t vl) {
+  return __riscv_vmnor_mm_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmnor_case_5(vbool32_t v1, size_t vl) {
+  return __riscv_vmnor_mm_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmnor_case_6(vbool64_t v1, size_t vl) {
+  return __riscv_vmnor_mm_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmorn_case_0(vbool1_t v1, size_t vl) {
+  return __riscv_vmorn_mm_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmorn_case_1(vbool2_t v1, size_t vl) {
+  return __riscv_vmorn_mm_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmorn_case_2(vbool4_t v1, size_t vl) {
+  return __riscv_vmorn_mm_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmorn_case_3(vbool8_t v1, size_t vl) {
+  return __riscv_vmorn_mm_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmorn_case_4(vbool16_t v1, size_t vl) {
+  return __riscv_vmorn_mm_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmorn_case_5(vbool32_t v1, size_t vl) {
+  return __riscv_vmorn_mm_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmorn_case_6(vbool64_t v1, size_t vl) {
+  return __riscv_vmorn_mm_b64(v1, v1, vl);
+}
+
+vbool1_t test_shortcut_for_riscv_vmxnor_case_0(vbool1_t v1, size_t vl) {
+  return __riscv_vmxnor_mm_b1(v1, v1, vl);
+}
+
+vbool2_t test_shortcut_for_riscv_vmxnor_case_1(vbool2_t v1, size_t vl) {
+  return __riscv_vmxnor_mm_b2(v1, v1, vl);
+}
+
+vbool4_t test_shortcut_for_riscv_vmxnor_case_2(vbool4_t v1, size_t vl) {
+  return __riscv_vmxnor_mm_b4(v1, v1, vl);
+}
+
+vbool8_t test_shortcut_for_riscv_vmxnor_case_3(vbool8_t v1, size_t vl) {
+  return __riscv_vmxnor_mm_b8(v1, v1, vl);
+}
+
+vbool16_t test_shortcut_for_riscv_vmxnor_case_4(vbool16_t v1, size_t vl) {
+  return __riscv_vmxnor_mm_b16(v1, v1, vl);
+}
+
+vbool32_t test_shortcut_for_riscv_vmxnor_case_5(vbool32_t v1, size_t vl) {
+  return __riscv_vmxnor_mm_b32(v1, v1, vl);
+}
+
+vbool64_t test_shortcut_for_riscv_vmxnor_case_6(vbool64_t v1, size_t vl) {
+  return __riscv_vmxnor_mm_b64(v1, v1, vl);
+}
+
+/* { dg-final { scan-assembler-not {vmand\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmnand\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmnandn\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-times {vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-not {vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
-- 
2.34.1
  

Sure thing, let me update it ASAP.

Pan

From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Friday, April 14, 2023 10:35 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Kito.cheng <kito.cheng@sifive.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; Li, Pan2 <pan2.li@intel.com>
Subject: Re: [PATCH] RISC-V: Add test cases for the RVV mask insn shortcut.


+/* { dg-final { scan-assembler-not {vmand\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmnand\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmnandn\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmxor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-not {vmnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */
+/* { dg-final { scan-assembler-times {vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 7 } } */
+/* { dg-final { scan-assembler-not {vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+} } } */

It's better add more assembler check
check how many vmclr.m or vmset.m should be.