From patchwork Mon Apr 10 14:48:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 81529 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1945571vqo; Mon, 10 Apr 2023 07:48:55 -0700 (PDT) X-Google-Smtp-Source: AKy350aNulbWTHX+wPKLBkMNfpyMRDdix6nLyPSXWTYQDXUF0vCPYBsWJ1/acJ1G/zsQrxjUgD+0 X-Received: by 2002:a17:907:728a:b0:947:6ce9:705d with SMTP id dt10-20020a170907728a00b009476ce9705dmr7785519ejc.55.1681138135536; Mon, 10 Apr 2023 07:48:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681138135; cv=none; d=google.com; s=arc-20160816; b=y4ne2ptUkPtVlaUmROijWpthzbt+Zj85FpzbnM5l+tb5+WHEfCrab4fYW4wyE6Q7f7 yCm98peUuf010+IrRSEM1F8oHbWisL7R6oC6PBCjdwyO6VpwwE47uFgWsWfqz2chkTLl WiYi/RNObSpvFenaGUujM3DGRqZcqLDUAgjSbk3mzXJgupX4IwBshREOKlUg11V3u45g chLocIELklss8KNEqS9NVihbQ6l6r+lRc9Wyti3aJk2zFRvK5r+fAkUK0w35vaHPObCG w+Ji03SJ4UqRrLFpCLAmOjMjDG/WZN2bAKAtysr5IE1mcdF9+ldaITzYTyNelfl7bkZO hSuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dmarc-filter:delivered-to; bh=I93on0KsHSJRuJFgy3cIbGWpwrjbRWdYqCLHwOV6Z0I=; b=IwswaKtBp06+SUlxs+BjGPk25FuHsW7OSpSA/ulJLnv8IWAlgj4jjmNBkXNl7MbeEU LeDfAvKKV5mc9kvn6fY4UiQRWT0ovl0niRnQkLt45UD2UZvLIxenUV+DqaNREo2M5ZNL zu4wu/m+lvy9AbTSG7MhC4mv/0cfTimh4A/cprJlWuY3pnpV4h8+nvvTt+f4lz3/I8tn B4Ki26cu/Rno2bDcmgasc6JRofHXg0zeR1rKHGsyYSRM/HNotFjv1LHPD+30pLLoXLfH ZtAdhXixdsADn7VCnWrJvn1E8m93Pv1RJPbhMk7OV4NeGlPR4tDeYnvy+eAz2JdlnQQW T28w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ud15-20020a170907c60f00b0094a55ce2d8bsi3958106ejc.606.2023.04.10.07.48.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 07:48:55 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8C3463858408 for ; Mon, 10 Apr 2023 14:48:51 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id 580F43858C5F for ; Mon, 10 Apr 2023 14:48:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 580F43858C5F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp62t1681138092tvp3bql5 Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 10 Apr 2023 22:48:10 +0800 (CST) X-QQ-SSF: 01400000000000F0O000000A0000000 X-QQ-FEAT: k0mQ4ihyJQN2vnZqNuUFUYDBMP+33ZOS1zkEkNtyM5iIdZ3FWL9/mZWhFJoNy sLFXO+uuda3rUG+isrq18RovnuJ2Dj6rH+uvqem2mp7kSXxb6XYYIj51XORmSqaB0/TZbcu prnlVCb+wdpDaUw5gIhqQHWhg/fYeUG6Hcirvo6u6wfoAIuCQl/r3qrYV2XbEwK+ciePpfg 4lJrst9zeDKC6x7alMyrO5yLhJuoW0guiMlQ/KmgmDMEMhbB8zlIonpcl4c/SEYiPRjtN17 eq1v4ihKKvaglRk8hhe9saWGlIPzTU6N+DLWWpIuMhkiY1NZFd/Nd7QNOtNXUOiTHnTcH7S urdHnO8AR7uhue+cDQmwXPzq9g6AD5fliaj21ZR1GFC0DdIxY5az8CZqttUWXTJ9zpaxD3v w6vxLm29eqs= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 7724129627318586145 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com, jakub@redhat.com, richard.sandiford@arm.com, rguenther@suse.de, Juzhe-Zhong Subject: [PATCH] machine_mode type size: Extend enum size from 8-bit to 16-bit Date: Mon, 10 Apr 2023 22:48:08 +0800 Message-Id: <20230410144808.324346-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762801101537881995?= X-GMAIL-MSGID: =?utf-8?q?1762801101537881995?= From: Juzhe-Zhong According RVV ISA: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-type-register-vtype We have LMUL: 1/8, 1/4, 1/2, 1, 2, 4, 8 Also, for segment instructions, we have tuple type for NF = 2 ~ 8. For example, for LMUL = 1/2, SEW = 32, we have vint32mf2_t, we will have NF from 2 ~ 8 tuples: vint32mf2x2_t, vint32mf2x2... vint32mf2x8_t. So we will end up with over 220+ vector machine mode for RVV. PLUS the scalar machine modes that we already have in RISC-V port. The total machine modes in RISC-V port > 256. Current GCC can not allow us support RVV segment instructions tuple types. So extend machine mode size from 8bit to 16bit. I have another solution related to this patch, May be adding a target dependent macro is better? Revise this patch like this: #ifdef TARGET_MAX_MACHINE_MODE_LARGER_THAN_256 ENUM_BITFIELD(machine_mode) last_set_mode : 16; #else ENUM_BITFIELD(machine_mode) last_set_mode : 8; #endif Not sure whether this solution is better? This patch Bootstraped on X86 is PASS. Will run make-check gcc-testsuite tomorrow. Expecting land in GCC-14, any suggestions ? gcc/ChangeLog: * combine.cc (struct reg_stat_type): Extend 8bit to 16bit. * cse.cc (struct qty_table_elem): Ditto. (struct table_elt): Ditto. (struct set): Ditto. * genopinit.cc (main): Ditto. * ira-int.h (struct ira_allocno): Ditto. * ree.cc (struct ATTRIBUTE_PACKED): Ditto. * rtl-ssa/accesses.h: Ditto. * rtl.h (struct GTY): Ditto. (subreg_shape::unique_id): Ditto. * rtlanal.h: Ditto. * tree-core.h (struct tree_type_common): Ditto. (struct tree_decl_common): Ditto. --- gcc/combine.cc | 4 ++-- gcc/cse.cc | 6 +++--- gcc/genopinit.cc | 2 +- gcc/ira-int.h | 4 ++-- gcc/ree.cc | 2 +- gcc/rtl-ssa/accesses.h | 2 +- gcc/rtl.h | 4 ++-- gcc/rtlanal.h | 2 +- gcc/tree-core.h | 4 ++-- 9 files changed, 15 insertions(+), 15 deletions(-) diff --git a/gcc/combine.cc b/gcc/combine.cc index 053879500b7..af9bae23c92 100644 --- a/gcc/combine.cc +++ b/gcc/combine.cc @@ -200,7 +200,7 @@ struct reg_stat_type { unsigned HOST_WIDE_INT last_set_nonzero_bits; char last_set_sign_bit_copies; - ENUM_BITFIELD(machine_mode) last_set_mode : 8; + ENUM_BITFIELD(machine_mode) last_set_mode : 16; /* Set nonzero if references to register n in expressions should not be used. last_set_invalid is set nonzero when this register is being @@ -235,7 +235,7 @@ struct reg_stat_type { truncation if we know that value already contains a truncated value. */ - ENUM_BITFIELD(machine_mode) truncated_to_mode : 8; + ENUM_BITFIELD(machine_mode) truncated_to_mode : 16; }; diff --git a/gcc/cse.cc b/gcc/cse.cc index 8fbda4ecc86..d78efaa39f7 100644 --- a/gcc/cse.cc +++ b/gcc/cse.cc @@ -251,7 +251,7 @@ struct qty_table_elem /* The sizes of these fields should match the sizes of the code and mode fields of struct rtx_def (see rtl.h). */ ENUM_BITFIELD(rtx_code) comparison_code : 16; - ENUM_BITFIELD(machine_mode) mode : 8; + ENUM_BITFIELD(machine_mode) mode : 16; }; /* The table of all qtys, indexed by qty number. */ @@ -406,7 +406,7 @@ struct table_elt int regcost; /* The size of this field should match the size of the mode field of struct rtx_def (see rtl.h). */ - ENUM_BITFIELD(machine_mode) mode : 8; + ENUM_BITFIELD(machine_mode) mode : 16; char in_memory; char is_const; char flag; @@ -4146,7 +4146,7 @@ struct set /* Original machine mode, in case it becomes a CONST_INT. The size of this field should match the size of the mode field of struct rtx_def (see rtl.h). */ - ENUM_BITFIELD(machine_mode) mode : 8; + ENUM_BITFIELD(machine_mode) mode : 16; /* Hash value of constant equivalent for SET_SRC. */ unsigned src_const_hash; /* A constant equivalent for SET_SRC, if any. */ diff --git a/gcc/genopinit.cc b/gcc/genopinit.cc index 83cb7504fa1..3ca3e9fd946 100644 --- a/gcc/genopinit.cc +++ b/gcc/genopinit.cc @@ -182,7 +182,7 @@ main (int argc, const char **argv) progname = "genopinit"; - if (NUM_OPTABS > 0xffff || MAX_MACHINE_MODE >= 0xff) + if (NUM_OPTABS > 0xffff || MAX_MACHINE_MODE >= 0xffff) fatal ("genopinit range assumptions invalid"); if (!init_rtx_reader_args_cb (argc, argv, handle_arg)) diff --git a/gcc/ira-int.h b/gcc/ira-int.h index e2de47213b4..65ec1678146 100644 --- a/gcc/ira-int.h +++ b/gcc/ira-int.h @@ -281,10 +281,10 @@ struct ira_allocno int regno; /* Mode of the allocno which is the mode of the corresponding pseudo-register. */ - ENUM_BITFIELD (machine_mode) mode : 8; + ENUM_BITFIELD (machine_mode) mode : 16; /* Widest mode of the allocno which in at least one case could be for paradoxical subregs where wmode > mode. */ - ENUM_BITFIELD (machine_mode) wmode : 8; + ENUM_BITFIELD (machine_mode) wmode : 16; /* Register class which should be used for allocation for given allocno. NO_REGS means that we should use memory. */ ENUM_BITFIELD (reg_class) aclass : 16; diff --git a/gcc/ree.cc b/gcc/ree.cc index 413aec7c8eb..e74b96cdfac 100644 --- a/gcc/ree.cc +++ b/gcc/ree.cc @@ -567,7 +567,7 @@ enum ext_modified_kind struct ATTRIBUTE_PACKED ext_modified { /* Mode from which ree has zero or sign extended the destination. */ - ENUM_BITFIELD(machine_mode) mode : 8; + ENUM_BITFIELD(machine_mode) mode : 16; /* Kind of modification of the insn. */ ENUM_BITFIELD(ext_modified_kind) kind : 2; diff --git a/gcc/rtl-ssa/accesses.h b/gcc/rtl-ssa/accesses.h index c5180b9308a..3c928058490 100644 --- a/gcc/rtl-ssa/accesses.h +++ b/gcc/rtl-ssa/accesses.h @@ -254,7 +254,7 @@ private: unsigned int m_spare : 2; // The value returned by the accessor above. - machine_mode m_mode : 8; + machine_mode m_mode : 16; }; // A contiguous array of access_info pointers. Used to represent a diff --git a/gcc/rtl.h b/gcc/rtl.h index 52f0419af29..c228c89da63 100644 --- a/gcc/rtl.h +++ b/gcc/rtl.h @@ -313,7 +313,7 @@ struct GTY((desc("0"), tag("0"), ENUM_BITFIELD(rtx_code) code: 16; /* The kind of value the expression has. */ - ENUM_BITFIELD(machine_mode) mode : 8; + ENUM_BITFIELD(machine_mode) mode : 16; /* 1 in a MEM if we should keep the alias set for this mem unchanged when we access a component. @@ -2157,7 +2157,7 @@ subreg_shape::operator != (const subreg_shape &other) const inline unsigned HOST_WIDE_INT subreg_shape::unique_id () const { - { STATIC_ASSERT (MAX_MACHINE_MODE <= 256); } + { STATIC_ASSERT (MAX_MACHINE_MODE <= 32768); } { STATIC_ASSERT (NUM_POLY_INT_COEFFS <= 3); } { STATIC_ASSERT (sizeof (offset.coeffs[0]) <= 2); } int res = (int) inner_mode + ((int) outer_mode << 8); diff --git a/gcc/rtlanal.h b/gcc/rtlanal.h index 5fbed816e20..bdd84e39c76 100644 --- a/gcc/rtlanal.h +++ b/gcc/rtlanal.h @@ -100,7 +100,7 @@ public: /* The mode of the reference. If IS_MULTIREG, this is the mode of REGNO - MULTIREG_OFFSET. */ - machine_mode mode : 8; + machine_mode mode : 16; /* If IS_MULTIREG, the offset of REGNO from the start of the register. */ unsigned int multireg_offset : 8; diff --git a/gcc/tree-core.h b/gcc/tree-core.h index fd2be57b78c..19d7c011530 100644 --- a/gcc/tree-core.h +++ b/gcc/tree-core.h @@ -1693,7 +1693,7 @@ struct GTY(()) tree_type_common { unsigned restrict_flag : 1; unsigned contains_placeholder_bits : 2; - ENUM_BITFIELD(machine_mode) mode : 8; + ENUM_BITFIELD(machine_mode) mode : 16; /* TYPE_STRING_FLAG for INTEGER_TYPE and ARRAY_TYPE. TYPE_CXX_ODR_P for RECORD_TYPE and UNION_TYPE. */ @@ -1776,7 +1776,7 @@ struct GTY(()) tree_decl_common { struct tree_decl_minimal common; tree size; - ENUM_BITFIELD(machine_mode) mode : 8; + ENUM_BITFIELD(machine_mode) mode : 16; unsigned nonlocal_flag : 1; unsigned virtual_flag : 1;