diff mbox series

RISC-V: Allow LMUL = 2 auto-vectorization for zve32*

Message ID 20230410033938.130469-1-juzhe.zhong@rivai.ai
State Unresolved
Headers
Series RISC-V: Allow LMUL = 2 auto-vectorization for zve32* |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

juzhe.zhong@rivai.ai April 10, 2023, 3:39 a.m. UTC 
  From: Juzhe-Zhong <juzhe.zhong@rivai.ai>

Since VNx1SI mode is nunits = [1,1] which will create ICE in
Loop vectorizer of GCC. We disabled it. The current condition
allows VNx4SI which LMUL = 4. We should be able to enable VNx2SI too.
This patch is to enable auto-vectorization for VNx2SImode.

gcc/ChangeLog:

        * config/riscv/riscv-v.cc (preferred_simd_mode): Enable LMUL = 2 auto-vectorization for TARGET_MIN_VLEN < 128.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/autovec/zve32f-3.c: Adapt testcase.
        * gcc.target/riscv/rvv/autovec/zve32x-3.c: Ditto.

---
 gcc/config/riscv/riscv-v.cc                           | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c | 4 ++--
 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 84d33fcdd14..801a4e26b67 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -761,7 +761,7 @@  preferred_simd_mode (scalar_mode mode)
 	 auto-vectorization since Loop Vectorizer may use VNx1SImode or
 	 VNx1DImode to vectorize which will create ICE in the
 	 'can_duplicate_and_interleave_p' of tree-vect-slp.cc.  */
-      if (TARGET_MIN_VLEN * riscv_autovec_lmul < 128)
+      if (TARGET_MIN_VLEN < 128 && riscv_autovec_lmul < RVV_M2)
 	return word_mode;
       /* We use LMUL = 1 as base bytesize which is BYTES_PER_RISCV_VECTOR and
 	 riscv_autovec_lmul as multiply factor to calculate the the NUNITS to
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
index 0c1aee23d25..8e68b9932b4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
@@ -1,6 +1,6 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */
+/* { dg-options "-march=rv32gc_zve32f -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */
 
 #include "template-1.h"
 
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 4 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
index 94593f43a62..c26c2c95afb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
@@ -1,6 +1,6 @@ 
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m4 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */
+/* { dg-options "-march=rv32gc_zve32x -mabi=ilp32d --param riscv-autovec-preference=fixed-vlmax --param riscv-autovec-lmul=m2 -O3 -ftree-vectorize -fdump-tree-vect-details -save-temps" } */
 
 #include "template-1.h"
 
-/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 2 "vect" } } */
+/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 3 "vect" } } */