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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id c3-20020aa7df03000000b005021f0d5762si1143330edy.681.2023.04.06.06.39.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Apr 2023 06:39:36 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=sZMxRpvr; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2E2DD3858436 for ; Thu, 6 Apr 2023 13:39:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2E2DD3858436 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1680788375; bh=5SZxx3oAwofujUzdjp82uBT4Q1U/xhuWaU4YQFk3Ocw=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=sZMxRpvrjLFUbm3XqRU7IImpRtg4t8yUPQTwwNl0/Eg5cnrYmaZKWTaMSb7RhwPjs sUYmmUMgMYPrUNdqJGcdcxp2lXMoUoz6KN17BxJQcWReSrissVW8K/bm9cyhSWhIIw abfPj+K6Bf21eWUV1WiTj40oEvURFaP+sxDwxTi8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id B39773858D28 for ; Thu, 6 Apr 2023 13:38:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B39773858D28 X-IronPort-AV: E=McAfee;i="6600,9927,10672"; a="326799769" X-IronPort-AV: E=Sophos;i="5.98,323,1673942400"; d="scan'208";a="326799769" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2023 06:37:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10672"; a="756375027" X-IronPort-AV: E=Sophos;i="5.98,323,1673942400"; d="scan'208";a="756375027" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga004.fm.intel.com with ESMTP; 06 Apr 2023 06:37:24 -0700 Received: from yanzhang-dev.sh.intel.com (yanzhang-dev.sh.intel.com [10.239.82.176]) by shvmail02.sh.intel.com (Postfix) with ESMTP id A387310057FB; Thu, 6 Apr 2023 21:37:23 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, yanzhang.wang@intel.com Subject: [PATCH] RISC-V: Fix regression of -fzero-call-used-regs=all Date: Thu, 6 Apr 2023 21:34:41 +0800 Message-Id: <20230406133441.1944365-1-yanzhang.wang@intel.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "yanzhang.wang--- via Gcc-patches" From: "Li, Pan2 via Gcc-patches" Reply-To: yanzhang.wang@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1762434352748316862?= X-GMAIL-MSGID: =?utf-8?q?1762434352748316862?= From: Yanzhang Wang This patch registers a riscv specific function to TARGET_ZERO_CALL_USED_REGS instead of default in targhooks.cc. It will clean gpr and vector relevant registers. PR 109104 gcc/ChangeLog: * config/riscv/riscv-v.cc (default_zero_call_used_regs): (riscv_zero_call_used_regs): * config/riscv/riscv.cc (riscv_zero_call_used_regs): (TARGET_ZERO_CALL_USED_REGS): gcc/testsuite/ChangeLog: * gcc.target/riscv/zero-scratch-regs-1.c: New test. * gcc.target/riscv/zero-scratch-regs-2.c: New test. Signed-off-by: Yanzhang Wang Co-authored-by: Pan Li Co-authored-by: Ju-Zhe Zhong Co-authored-by: Kito Cheng Signed-off-by: Yanzhang Wang --- gcc/config/riscv/riscv-v.cc | 79 +++++++++++++++++++ gcc/config/riscv/riscv.cc | 6 ++ .../gcc.target/riscv/zero-scratch-regs-1.c | 9 +++ .../gcc.target/riscv/zero-scratch-regs-2.c | 24 ++++++ 4 files changed, 118 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 2e91d019f6c..90c69b52bb4 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -43,6 +43,7 @@ #include "optabs.h" #include "tm-constrs.h" #include "rtx-vector-builder.h" +#include "diagnostic-core.h" using namespace riscv_vector; @@ -724,4 +725,82 @@ gen_avl_for_scalar_move (rtx avl) } } +/* Generate a sequence of instructions that zero registers specified by + NEED_ZEROED_HARDREGS. Return the ZEROED_HARDREGS that are actually + zeroed. */ +static HARD_REG_SET +gpr_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) +{ + HARD_REG_SET zeroed_hardregs; + CLEAR_HARD_REG_SET (zeroed_hardregs); + + for (unsigned regno = GP_REG_FIRST; regno <= GP_REG_LAST; ++regno) + { + if (!TEST_HARD_REG_BIT (need_zeroed_hardregs, regno)) + continue; + + rtx reg = regno_reg_rtx[regno]; + machine_mode mode = GET_MODE (reg); + emit_move_insn (reg, CONST0_RTX (mode)); + + SET_HARD_REG_BIT (zeroed_hardregs, regno); + } + + return zeroed_hardregs; +} + +static HARD_REG_SET +vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) +{ + HARD_REG_SET zeroed_hardregs; + CLEAR_HARD_REG_SET (zeroed_hardregs); + + /* Find a register to hold vl. */ + unsigned vl_regno = GP_REG_LAST + 1; + for (unsigned regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) + { + /* If vl and avl both are x0, the existing vl is kept. */ + if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno) && regno != X0_REGNUM) + { + vl_regno = regno; + break; + } + } + + if (vl_regno > GP_REG_LAST) + sorry ("can't allocate vl register for %qs on this target", + "-fzero-call-used-regs"); + + rtx vl = gen_rtx_REG (Pmode, vl_regno); /* vl is VLMAX. */ + for (unsigned regno = V_REG_FIRST; regno <= V_REG_LAST; ++regno) + { + if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno)) + { + rtx target = regno_reg_rtx[regno]; + machine_mode mode = GET_MODE (target); + poly_uint16 nunits = GET_MODE_NUNITS (mode); + machine_mode mask_mode = get_vector_mode (BImode, nunits).require (); + + emit_vlmax_vsetvl (mode, vl); + emit_vlmax_op (code_for_pred_mov (mode), target, CONST0_RTX (mode), + vl, mask_mode); + + SET_HARD_REG_BIT (zeroed_hardregs, regno); + } + } + + return zeroed_hardregs; +} + +HARD_REG_SET +riscv_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) +{ + HARD_REG_SET zeroed_hardregs; + CLEAR_HARD_REG_SET (zeroed_hardregs); + + if (TARGET_VECTOR) + zeroed_hardregs |= vector_zero_call_used_regs (need_zeroed_hardregs); + + return zeroed_hardregs | gpr_zero_call_used_regs (need_zeroed_hardregs); +} } // namespace riscv_vector diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 5f542932d13..e176f2d9f34 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7317,6 +7317,12 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask) #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE #define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value +namespace riscv_vector { +extern HARD_REG_SET riscv_zero_call_used_regs (HARD_REG_SET); +} +#undef TARGET_ZERO_CALL_USED_REGS +#define TARGET_ZERO_CALL_USED_REGS riscv_vector::riscv_zero_call_used_regs + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-riscv.h" diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c new file mode 100644 index 00000000000..2d9dfeb9dc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fzero-call-used-regs=used -fno-stack-protector -fno-PIC" } */ + +void +foo (void) +{ +} + +/* { dg-final { scan-assembler-not "li\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c new file mode 100644 index 00000000000..a53f034b5d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zero-scratch-regs-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fzero-call-used-regs=all-gpr" } */ + +void +foo (void) +{ +} + +/* { dg-final { scan-assembler-not "vsetvli" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t0,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t1,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t2,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a0,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a1,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a2,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a3,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a4,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a5,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a6,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*a7,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t3,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t4,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t5,0" } } */ +/* { dg-final { scan-assembler "li\[ \t\]*t6,0" } } */