diff mbox series

[v2,8/8] RISCV: Weaken mem_thread_fence

Message ID 20230405210118.1969283-9-patrick@rivosinc.com
State Accepted
Headers
Series RISCV: Implement ISA Manual Table A.6 Mappings |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Patrick O'Neill April 5, 2023, 9:01 p.m. UTC 
  This change brings atomic fences in line with table A.6 of the ISA
manual.

Relax mem_thread_fence according to the memmodel given.

2023-04-05 Patrick O'Neill <patrick@rivosinc.com>

	* riscv.cc: Expose helper functions to sync.md.
	* riscv-protos.h: Likewise.
	* sync.md (mem_thread_fence_1): Change fence depending on
	aquire/release requirements.
	* amo-thread-fence-1: New test.
	* amo-thread-fence-2: Likewise.
	* amo-thread-fence-3: Likewise.
	* amo-thread-fence-4: Likewise.
	* amo-thread-fence-5: Likewise.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
---
 gcc/config/riscv/riscv-protos.h                 |  2 ++
 gcc/config/riscv/riscv.cc                       |  4 ++--
 gcc/config/riscv/sync.md                        | 17 ++++++++++++++---
 .../gcc.target/riscv/amo-thread-fence-1.c       |  6 ++++++
 .../gcc.target/riscv/amo-thread-fence-2.c       |  6 ++++++
 .../gcc.target/riscv/amo-thread-fence-3.c       |  6 ++++++
 .../gcc.target/riscv/amo-thread-fence-4.c       |  6 ++++++
 .../gcc.target/riscv/amo-thread-fence-5.c       |  6 ++++++
 8 files changed, 48 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index b03edc3e8a5..233b8070047 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -81,6 +81,8 @@  extern void riscv_reinit (void);
 extern poly_uint64 riscv_regmode_natural_size (machine_mode);
 extern bool riscv_v_ext_vector_mode_p (machine_mode);
 extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT);
+extern bool riscv_memmodel_needs_amo_acquire (enum memmodel);
+extern bool riscv_memmodel_needs_amo_release (enum memmodel);
 extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel);
 
 /* Routines implemented in riscv-c.cc.  */
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 061d2cf42b4..27d876ac44c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4311,7 +4311,7 @@  riscv_union_memmodels (enum memmodel model1, enum memmodel model2)
 /* Return true if the .AQ suffix should be added to an AMO to implement the
    acquire portion of memory model MODEL.  */
 
-static bool
+bool
 riscv_memmodel_needs_amo_acquire (enum memmodel model)
 {
   switch (model)
@@ -4334,7 +4334,7 @@  riscv_memmodel_needs_amo_acquire (enum memmodel model)
 /* Return true if the .RL suffix should be added to an AMO to implement the
    release portion of memory model MODEL.  */
 
-static bool
+bool
 riscv_memmodel_needs_amo_release (enum memmodel model)
 {
   switch (model)
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index cdd227721e1..4204c956bd6 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -42,14 +42,25 @@ 
   DONE;
 })
 
-;; Until the RISC-V memory model (hence its mapping from C++) is finalized,
-;; conservatively emit a full FENCE.
 (define_insn "mem_thread_fence_1"
   [(set (match_operand:BLK 0 "" "")
 	(unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
    (match_operand:SI 1 "const_int_operand" "")] ;; model
   ""
-  "fence\tiorw,iorw")
+  {
+    enum memmodel model = (enum memmodel) INTVAL (operands[1]);
+    model = memmodel_base (model);
+    if (model == MEMMODEL_ACQ_REL)
+	return "fence.tso";
+    else if (riscv_memmodel_needs_amo_acquire (model) &&
+	     riscv_memmodel_needs_amo_release (model))
+	return "fence\trw,rw";
+    else if (riscv_memmodel_needs_amo_acquire (model))
+	return "fence\tr,rw";
+    else if (riscv_memmodel_needs_amo_release (model))
+	return "fence\trw,w";
+  }
+  [(set (attr "length") (const_int 4))])
 
 ;; Atomic memory operations.
 
diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c
new file mode 100644
index 00000000000..833629bf2f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-1.c
@@ -0,0 +1,6 @@ 
+/* { dg-do compile } */
+/* { dg-final { scan-assembler-not "fence\t" } } */
+
+int main() {
+  __atomic_thread_fence(__ATOMIC_RELAXED);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c
new file mode 100644
index 00000000000..3395ee41dbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-2.c
@@ -0,0 +1,6 @@ 
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "fence\tr,rw" } } */
+
+int main() {
+  __atomic_thread_fence(__ATOMIC_ACQUIRE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c
new file mode 100644
index 00000000000..59cc4e5d394
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-3.c
@@ -0,0 +1,6 @@ 
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "fence\trw,w" } } */
+
+int main() {
+  __atomic_thread_fence(__ATOMIC_RELEASE);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c
new file mode 100644
index 00000000000..2afed9a9e38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-4.c
@@ -0,0 +1,6 @@ 
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "fence.tso" } } */
+
+int main() {
+  __atomic_thread_fence(__ATOMIC_ACQ_REL);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c
new file mode 100644
index 00000000000..b8d56c0f066
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo-thread-fence-5.c
@@ -0,0 +1,6 @@ 
+/* { dg-do compile } */
+/* { dg-final { scan-assembler "fence\trw,rw" } } */
+
+int main() {
+  __atomic_thread_fence(__ATOMIC_SEQ_CST);
+}