diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index e41f65a0894..4611447ddde 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -205,6 +205,7 @@ enum vlen_enum
 };
 bool slide1_sew64_helper (int, machine_mode, machine_mode,
 			  machine_mode, rtx *);
+rtx gen_avl_for_scalar_move (rtx);
 }
 
 /* We classify builtin types into two classes:
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index d7b77fd6123..968db0831f1 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -701,4 +701,23 @@ slide1_sew64_helper (int unspec, machine_mode mode, machine_mode demote_mode,
   return true;
 }
 
+rtx
+gen_avl_for_scalar_move (rtx avl)
+{
+  if (CONST_INT_P (avl))
+    {
+      if (rtx_equal_p (avl, const0_rtx))
+	return const0_rtx;
+      else
+	return const1_rtx;
+    }
+  else
+    {
+      rtx tmp = gen_reg_rtx (Pmode);
+      emit_insn (
+	gen_rtx_SET (tmp, gen_rtx_fmt_ee (GTU, Pmode, avl, const0_rtx)));
+      return tmp;
+    }
+}
+
 } // namespace riscv_vector
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 52597750f69..6c8e046bd29 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1229,9 +1229,7 @@
           else if (GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode))
             {
 	      // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system.
-	      rtx tmp = gen_reg_rtx (Pmode);
-              emit_insn (gen_rtx_SET (tmp, gen_rtx_AND (Pmode, operands[4], const1_rtx)));
-	      operands[4] = tmp;
+	      operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
 	      operands[1] = CONSTM1_RTX (<VM>mode);
 	    }
           else
@@ -1292,9 +1290,7 @@
        vlse64.v  */
     if (satisfies_constraint_Wb1 (operands[1]))
       {
-	rtx tmp = gen_reg_rtx (Pmode);
-        emit_insn (gen_rtx_SET (tmp, gen_rtx_AND (Pmode, operands[4], const1_rtx)));
-        operands[4] = tmp;
+	operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
 	operands[1] = CONSTM1_RTX (<VM>mode);
       }
   }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c
index 268ddd7c116..f27f85cdb58 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c
@@ -37,8 +37,6 @@ void foo2 (void *base, void *out, size_t vl)
 /*
 ** foo3:
 ** ...
-** andi\t[a-x0-9]+,\s*[a-x0-9]+,\s*1
-** ...
 ** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero
 ** ...
 ** ret
@@ -54,8 +52,6 @@ void foo3 (void *base, void *out, size_t vl)
 /*
 ** foo4:
 ** ...
-** andi\t[a-x0-9]+,\s*[a-x0-9]+,\s*1
-** ...
 ** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero
 ** ...
 ** ret
@@ -137,8 +133,6 @@ void foo9 (void *base, void *out, size_t vl)
 /*
 ** foo10:
 ** ...
-** andi\t[a-x0-9]+,\s*[a-x0-9]+,\s*1
-** ...
 ** vmv.v.i\tv[0-9]+,\s*-15
 ** ...
 */
@@ -167,8 +161,6 @@ void foo11 (void *base, void *out, size_t vl)
 /*
 ** foo12:
 ** ...
-** andi\t[a-x0-9]+,\s*[a-x0-9]+,\s*1
-** ...
 ** vmv.v.i\tv[0-9]+,\s*0
 ** ...
 ** ret
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
new file mode 100644
index 00000000000..80ee1b5f0c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3" } */
+
+#include "riscv_vector.h"
+
+vuint64m2_t f1(vuint64m2_t var_17, uint64_t var_60)
+{
+  vuint64m2_t var_16 = __riscv_vmv_s_x_u64m2_tu(var_17,var_60, 0);
+  return var_16;
+}
+
+vuint64m2_t f2(vuint64m2_t var_17, uint64_t var_60)
+{
+  vuint64m2_t var_16 = __riscv_vmv_s_x_u64m2_tu(var_17,var_60, 4);
+  return var_16;
+}
+
+vuint64m2_t f3(vuint64m2_t var_17, uint64_t var_60, size_t vl)
+{
+  vuint64m2_t var_16 = __riscv_vmv_s_x_u64m2_tu(var_17,var_60, vl);
+  return var_16;
+}
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*0,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 } } */
+/* { dg-final { scan-assembler-times {sgtu} 1 } } */
