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[8.43.85.97]) by mx.google.com with ESMTPS id j4-20020a1709062a0400b0093c1b6a0a85si16132721eje.356.2023.03.28.19.44.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 19:44:00 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 93604385703F for ; Wed, 29 Mar 2023 02:43:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg156.qq.com (smtpbg156.qq.com [15.184.82.18]) by sourceware.org (Postfix) with ESMTPS id E5D313858C50 for ; Wed, 29 Mar 2023 02:43:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E5D313858C50 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp76t1680057801t4m5i4e0 Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 29 Mar 2023 10:43:20 +0800 (CST) X-QQ-SSF: 01400000000000E0O000000A0000000 X-QQ-FEAT: QityeSR92A3eAd1he9qqdQxNjDm0+MqPfl+wtFqMit0fHgbPZWxNwoLgqOhMI LofxLgHWO/iKRVYG/W40bWZI3iN36BNd6K+ZjsEz2VaMiiYfiJyQS3dUPpa9PINJz/r+AE7 Hd3TIo/H9T/JSV3ULvbVrqCrR6eAD4qDwKpMsDzoIbE34c2CIMa2SZp99nXqgI6JTBn2DSG DoG7FCHAscOI3zPJP36aj5kcEeLhZH6Vt0P/iGegBkRMX21Zz1dZLhnwAbjsQKdOsto/RRK Vgw8kFO7yHcl+hWXkJbx7vdQ98o6m9xXkIolRONrvXu7Wco2qWczdDhyPTXeijSuLYeiJNR kUh4oQebj5k/uUxo6iCsREXK4ehRl+xcyK3WTUbDIJHXuQOCCE= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 7962011325267464794 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix ICE && codegen error of scalar move in RV32 system. Date: Wed, 29 Mar 2023 10:42:59 +0800 Message-Id: <20230329024259.174803-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761668329794104587?= X-GMAIL-MSGID: =?utf-8?q?1761668329794104587?= From: Juzhe-Zhong bug.C:144:2: error: unrecognizable insn: 144 | } | ^ (insn 684 683 685 26 (set (reg:SI 513) (and:SI (const_int 4 [0x4]) (const_int 1 [0x1]))) "bug.C":115:47 -1 (nil)) andi a4,a4,1 ===> sgtu a4,a4,zero vsetlvi tu vsetvli tu vlse vlse gcc/ChangeLog: * config/riscv/riscv-protos.h (gen_avl_for_scalar_move): New function. * config/riscv/riscv-v.cc (gen_avl_for_scalar_move): New function. * config/riscv/vector.md: Fix scalar move bug. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/scalar_move-6.c: Adapt test. * gcc.target/riscv/rvv/base/scalar_move-9.c: New test. --- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 19 ++++++++++++++ gcc/config/riscv/vector.md | 8 ++---- .../gcc.target/riscv/rvv/base/scalar_move-6.c | 8 ------ .../gcc.target/riscv/rvv/base/scalar_move-9.c | 26 +++++++++++++++++++ 5 files changed, 48 insertions(+), 14 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index e41f65a0894..4611447ddde 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -205,6 +205,7 @@ enum vlen_enum }; bool slide1_sew64_helper (int, machine_mode, machine_mode, machine_mode, rtx *); +rtx gen_avl_for_scalar_move (rtx); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index d7b77fd6123..968db0831f1 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -701,4 +701,23 @@ slide1_sew64_helper (int unspec, machine_mode mode, machine_mode demote_mode, return true; } +rtx +gen_avl_for_scalar_move (rtx avl) +{ + if (CONST_INT_P (avl)) + { + if (rtx_equal_p (avl, const0_rtx)) + return const0_rtx; + else + return const1_rtx; + } + else + { + rtx tmp = gen_reg_rtx (Pmode); + emit_insn ( + gen_rtx_SET (tmp, gen_rtx_fmt_ee (GTU, Pmode, avl, const0_rtx))); + return tmp; + } +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 52597750f69..6c8e046bd29 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1229,9 +1229,7 @@ else if (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (Pmode)) { // Case 2: vmv.s.x (TU) ==> andi vl + vlse.v (TU) in RV32 system. - rtx tmp = gen_reg_rtx (Pmode); - emit_insn (gen_rtx_SET (tmp, gen_rtx_AND (Pmode, operands[4], const1_rtx))); - operands[4] = tmp; + operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]); operands[1] = CONSTM1_RTX (mode); } else @@ -1292,9 +1290,7 @@ vlse64.v */ if (satisfies_constraint_Wb1 (operands[1])) { - rtx tmp = gen_reg_rtx (Pmode); - emit_insn (gen_rtx_SET (tmp, gen_rtx_AND (Pmode, operands[4], const1_rtx))); - operands[4] = tmp; + operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]); operands[1] = CONSTM1_RTX (mode); } } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c index 268ddd7c116..f27f85cdb58 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c @@ -37,8 +37,6 @@ void foo2 (void *base, void *out, size_t vl) /* ** foo3: ** ... -** andi\t[a-x0-9]+,\s*[a-x0-9]+,\s*1 -** ... ** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero ** ... ** ret @@ -54,8 +52,6 @@ void foo3 (void *base, void *out, size_t vl) /* ** foo4: ** ... -** andi\t[a-x0-9]+,\s*[a-x0-9]+,\s*1 -** ... ** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero ** ... ** ret @@ -137,8 +133,6 @@ void foo9 (void *base, void *out, size_t vl) /* ** foo10: ** ... -** andi\t[a-x0-9]+,\s*[a-x0-9]+,\s*1 -** ... ** vmv.v.i\tv[0-9]+,\s*-15 ** ... */ @@ -167,8 +161,6 @@ void foo11 (void *base, void *out, size_t vl) /* ** foo12: ** ... -** andi\t[a-x0-9]+,\s*[a-x0-9]+,\s*1 -** ... ** vmv.v.i\tv[0-9]+,\s*0 ** ... ** ret diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c new file mode 100644 index 00000000000..80ee1b5f0c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3" } */ + +#include "riscv_vector.h" + +vuint64m2_t f1(vuint64m2_t var_17, uint64_t var_60) +{ + vuint64m2_t var_16 = __riscv_vmv_s_x_u64m2_tu(var_17,var_60, 0); + return var_16; +} + +vuint64m2_t f2(vuint64m2_t var_17, uint64_t var_60) +{ + vuint64m2_t var_16 = __riscv_vmv_s_x_u64m2_tu(var_17,var_60, 4); + return var_16; +} + +vuint64m2_t f3(vuint64m2_t var_17, uint64_t var_60, size_t vl) +{ + vuint64m2_t var_16 = __riscv_vmv_s_x_u64m2_tu(var_17,var_60, vl); + return var_16; +} + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*0,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 } } */ +/* { dg-final { scan-assembler-times {sgtu} 1 } } */