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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id vx4-20020a170907a78400b00933063273a9si16698606ejc.455.2023.03.23.18.54.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 18:54:11 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CD9B338708E2 for ; Fri, 24 Mar 2023 01:53:39 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from zg8tndyumtaxlji0oc4xnzya.icoremail.net (zg8tndyumtaxlji0oc4xnzya.icoremail.net [46.101.248.176]) by sourceware.org (Postfix) with ESMTP id 5F74D3858D28 for ; Fri, 24 Mar 2023 01:53:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5F74D3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from localhost.localdomain (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id EwgMCgDnhMRzAh1kF0EAAA--.1238S4; Fri, 24 Mar 2023 09:52:51 +0800 (CST) From: Feng Wang To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Feng Wang Subject: [PATCH] RISC-V: Optimize load memory data in rv64 Date: Fri, 24 Mar 2023 01:52:39 +0000 Message-Id: <20230324015239.13455-1-wangfeng@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: EwgMCgDnhMRzAh1kF0EAAA--.1238S4 X-Coremail-Antispam: 1UD129KBjvJXoWxGFy3Kry8XF45ur48Jr1kXwb_yoW5Zr1Upa 1UGw4Yka97JFZxGr1fKF18Jw1rXwsagF98u3s7Zr12kF4rtrZ0vF1kKw13Ar43Ga10gr13 uayq9a43uw1F93DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkF14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4U JVW0owA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE-syl42xK 82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGw C20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48J MIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMI IF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E 87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x0JUywZ7UUUUU= X-CM-SenderInfo: pzdqwwxhqjqvxvzl0uprps33xlqjhudrp/ X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761212211276895580?= X-GMAIL-MSGID: =?utf-8?q?1761212211276895580?= This patch optimize load one byte or halfword from memory in rv64. Please refer to the following test case for loading one byte. int sextb32_memory(int* x) { return (*x << 24) >> 24; } The build flags are "-march=rv64g -mabi=lp64d -O2" The current compilation results are as follows, slliw a0,a0,0x18 sraiw a0,a0,0x18 ret The compilation results after picking this patch are as follows, lb a0,0(a0) ret The iusse is introduced by this patch "RISC-V: Avoid zero/sign extend for volatile loads. Fix for 97417." This patch expand (set (reg:QI/HI/SI target) (mem:QI/HI/SI (address))) to (set (reg:DI temp) (zero_extend:DI (mem:QI/HI/SI (address)))) (set (reg:QI/HI/SI target) (subreg:QI/HI/SI (reg:DI temp) 0)) There is no problem with this transformation for QI and HI. However,it will affect the subsequent combine processing for SI. So I modified this operation to only take effect for QI and HI. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_move):Modify length judgment gcc/testsuite/ChangeLog: * gcc.target/riscv/rv64-load-byte.c: New test. * gcc.target/riscv/rv64-load-halfword.c: New test. --- gcc/config/riscv/riscv.cc | 2 +- gcc/testsuite/gcc.target/riscv/rv64-load-byte.c | 8 ++++++++ gcc/testsuite/gcc.target/riscv/rv64-load-halfword.c | 8 ++++++++ 3 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rv64-load-byte.c create mode 100644 gcc/testsuite/gcc.target/riscv/rv64-load-halfword.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 1db12091b5a..4b596c7bb5b 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2074,7 +2074,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) (set (reg:QI target) (subreg:QI (reg:DI temp) 0)) with auto-sign/zero extend. */ if (GET_MODE_CLASS (mode) == MODE_INT - && GET_MODE_SIZE (mode).to_constant () < UNITS_PER_WORD + && GET_MODE_SIZE (mode).to_constant () < MIN_UNITS_PER_WORD && can_create_pseudo_p () && MEM_P (src)) { diff --git a/gcc/testsuite/gcc.target/riscv/rv64-load-byte.c b/gcc/testsuite/gcc.target/riscv/rv64-load-byte.c new file mode 100644 index 00000000000..929aac79993 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rv64-load-byte.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -O2" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +int sextb32_memory(int* x) +{ return (*x << 24) >> 24; } + +/* { dg-final { scan-assembler "lb" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rv64-load-halfword.c b/gcc/testsuite/gcc.target/riscv/rv64-load-halfword.c new file mode 100644 index 00000000000..94e1bd7e135 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rv64-load-halfword.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g -mabi=lp64d -O2" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +int sexth32_memory(int* x) +{ return (*x << 16) >> 16; } + +/* { dg-final { scan-assembler "lh" } } */