diff mbox series

RISC-V: Optimize load memory data in rv64

Message ID 20230324015239.13455-1-wangfeng@eswincomputing.com
State Accepted
Headers
Series RISC-V: Optimize load memory data in rv64 |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Feng Wang March 24, 2023, 1:52 a.m. UTC 
  This patch optimize load one byte or halfword from memory in rv64.
Please refer to the following test case for loading one byte.
int sextb32_memory(int* x)
{ return (*x << 24) >> 24; }

The build flags are "-march=rv64g -mabi=lp64d -O2"
The current compilation results are as follows,

slliw a0,a0,0x18
sraiw a0,a0,0x18
ret

The compilation results after picking this patch are as follows,
lb a0,0(a0)
ret

The iusse is introduced by this patch
"RISC-V: Avoid zero/sign extend for volatile loads. Fix for 97417."
This patch expand
(set (reg:QI/HI/SI target) (mem:QI/HI/SI (address)))
to
(set (reg:DI temp) (zero_extend:DI (mem:QI/HI/SI (address))))
(set (reg:QI/HI/SI target) (subreg:QI/HI/SI (reg:DI temp) 0))
There is no problem with this transformation for QI and HI.
However,it will affect the subsequent combine processing for SI.
So I modified this operation to only take effect for QI and HI.

gcc/ChangeLog:

        * config/riscv/riscv.cc (riscv_legitimize_move):Modify length judgment

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rv64-load-byte.c: New test.
        * gcc.target/riscv/rv64-load-halfword.c: New test.
---
 gcc/config/riscv/riscv.cc                           | 2 +-
 gcc/testsuite/gcc.target/riscv/rv64-load-byte.c     | 8 ++++++++
 gcc/testsuite/gcc.target/riscv/rv64-load-halfword.c | 8 ++++++++
 3 files changed, 17 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rv64-load-byte.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rv64-load-halfword.c
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 1db12091b5a..4b596c7bb5b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2074,7 +2074,7 @@  riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
        (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
      with auto-sign/zero extend.  */
   if (GET_MODE_CLASS (mode) == MODE_INT
-      && GET_MODE_SIZE (mode).to_constant () < UNITS_PER_WORD
+      && GET_MODE_SIZE (mode).to_constant () < MIN_UNITS_PER_WORD
       && can_create_pseudo_p ()
       && MEM_P (src))
     {
diff --git a/gcc/testsuite/gcc.target/riscv/rv64-load-byte.c b/gcc/testsuite/gcc.target/riscv/rv64-load-byte.c
new file mode 100644
index 00000000000..929aac79993
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rv64-load-byte.c
@@ -0,0 +1,8 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+int sextb32_memory(int* x)
+{ return (*x << 24) >> 24; }
+
+/* { dg-final { scan-assembler "lb" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rv64-load-halfword.c b/gcc/testsuite/gcc.target/riscv/rv64-load-halfword.c
new file mode 100644
index 00000000000..94e1bd7e135
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rv64-load-halfword.c
@@ -0,0 +1,8 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+int sexth32_memory(int* x)
+{ return (*x << 16) >> 16; }
+
+/* { dg-final { scan-assembler "lh" } } */