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[8.43.85.97]) by mx.google.com with ESMTPS id y17-20020aa7ccd1000000b004fcecd85fe7si15254413edt.77.2023.03.21.19.59.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 19:59:52 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=nLZoK8Ol; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 30EC63858421 for ; Wed, 22 Mar 2023 02:59:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 30EC63858421 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1679453991; bh=+yZ7jMJEPELQN/n4wr75NSAsKYlagrYoQrH5u/nrGZc=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=nLZoK8OlLgXN2NLhdC6jZ9WoW1oAwBQ3i+yU3PG92R2+zUB1w4jg0J6OxJzAKD77s BycPwi9RnhOWxa0z/M0vvZj5iAf5lnRr0NxN3WcDkjE3KUkekzoTSjtYLtGj1V4bUO +24rAbDb/lpnnD4/jaXXsTctVwvbCG6ted+X8pVs= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 868893858D38 for ; Wed, 22 Mar 2023 02:59:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 868893858D38 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="336618851" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="336618851" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2023 19:59:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10656"; a="659032811" X-IronPort-AV: E=Sophos;i="5.98,280,1673942400"; d="scan'208";a="659032811" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga006.jf.intel.com with ESMTP; 21 Mar 2023 19:59:02 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 067C910054DE; Wed, 22 Mar 2023 10:59:02 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com, ubizjak@gmail.com Subject: [PATCH] Remove TARGET_GEN_MEMSET_SCRATCH_RTX since it's not used anymore. Date: Wed, 22 Mar 2023 10:57:01 +0800 Message-Id: <20230322025701.3369256-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.39.1.388.g2fc9e9ca3c MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761035149423455569?= X-GMAIL-MSGID: =?utf-8?q?1761035149423455569?= The target hook is only used by i386, and the current definition is same as default gen_reg_rtx. So there's no need for this target hook. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ok for trunk(or GCC14)? gcc/ChangeLog: * builtins.cc (builtin_memset_read_str): Replace targetm.gen_memset_scratch_rtx with gen_reg_rtx. (builtin_memset_gen_str): Ditto. * config/i386/i386-expand.cc (ix86_convert_const_wide_int_to_broadcast): Replace ix86_gen_scratch_sse_rtx with gen_reg_rtx. (ix86_expand_vector_move): Ditto. * config/i386/i386-protos.h (ix86_gen_scratch_sse_rtx): Removed. * config/i386/i386.cc (ix86_gen_scratch_sse_rtx): Removed. (TARGET_GEN_MEMSET_SCRATCH_RTX): Removed. * doc/tm.texi: Remove TARGET_GEN_MEMSET_SCRATCH_RTX. * doc/tm.texi.in: Ditto. * target.def: Ditto. --- gcc/builtins.cc | 4 ++-- gcc/config/i386/i386-expand.cc | 6 +++--- gcc/config/i386/i386-protos.h | 2 -- gcc/config/i386/i386.cc | 12 ------------ gcc/doc/tm.texi | 7 ------- gcc/doc/tm.texi.in | 2 -- gcc/target.def | 9 --------- 7 files changed, 5 insertions(+), 37 deletions(-) diff --git a/gcc/builtins.cc b/gcc/builtins.cc index 90246e214d6..8026e2001b7 100644 --- a/gcc/builtins.cc +++ b/gcc/builtins.cc @@ -4212,7 +4212,7 @@ builtin_memset_read_str (void *data, void *prev, return const_vec; /* Use the move expander with CONST_VECTOR. */ - target = targetm.gen_memset_scratch_rtx (mode); + target = gen_reg_rtx (mode); emit_move_insn (target, const_vec); return target; } @@ -4256,7 +4256,7 @@ builtin_memset_gen_str (void *data, void *prev, the memset expander. */ insn_code icode = optab_handler (vec_duplicate_optab, mode); - target = targetm.gen_memset_scratch_rtx (mode); + target = gen_reg_rtx (mode); class expand_operand ops[2]; create_output_operand (&ops[0], target, mode); create_input_operand (&ops[1], (rtx) data, QImode); diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index c1300dc4e26..1e3ce4b7c3f 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -338,7 +338,7 @@ ix86_convert_const_wide_int_to_broadcast (machine_mode mode, rtx op) machine_mode vector_mode; if (!mode_for_vector (broadcast_mode, nunits).exists (&vector_mode)) gcc_unreachable (); - rtx target = ix86_gen_scratch_sse_rtx (vector_mode); + rtx target = gen_reg_rtx (vector_mode); bool ok = ix86_expand_vector_init_duplicate (false, vector_mode, target, GEN_INT (val_broadcast)); @@ -686,7 +686,7 @@ ix86_expand_vector_move (machine_mode mode, rtx operands[]) if (!register_operand (op0, mode) && !register_operand (op1, mode)) { - rtx scratch = ix86_gen_scratch_sse_rtx (mode); + rtx scratch = gen_reg_rtx (mode); emit_move_insn (scratch, op1); op1 = scratch; } @@ -728,7 +728,7 @@ ix86_expand_vector_move (machine_mode mode, rtx operands[]) && !register_operand (op0, mode) && !register_operand (op1, mode)) { - rtx tmp = ix86_gen_scratch_sse_rtx (GET_MODE (op0)); + rtx tmp = gen_reg_rtx (GET_MODE (op0)); emit_move_insn (tmp, op1); emit_move_insn (op0, tmp); return; diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index bfb2198265a..71ae95ffef7 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -50,8 +50,6 @@ extern void ix86_reset_previous_fndecl (void); extern bool ix86_using_red_zone (void); -extern rtx ix86_gen_scratch_sse_rtx (machine_mode); - extern unsigned int ix86_regmode_natural_size (machine_mode); extern bool ix86_check_builtin_isa_match (unsigned int fcode); #ifdef RTX_CODE diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 5d0e4739a84..6a8734c2346 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -24197,15 +24197,6 @@ ix86_optab_supported_p (int op, machine_mode mode1, machine_mode, } } -/* Implement the TARGET_GEN_MEMSET_SCRATCH_RTX hook. Return a scratch - register in MODE for vector load and store. */ - -rtx -ix86_gen_scratch_sse_rtx (machine_mode mode) -{ - return gen_reg_rtx (mode); -} - /* Address space support. This is not "far pointers" in the 16-bit sense, but an easy way @@ -25253,9 +25244,6 @@ static bool ix86_libc_has_fast_function (int fcode ATTRIBUTE_UNUSED) #undef TARGET_LIBC_HAS_FAST_FUNCTION #define TARGET_LIBC_HAS_FAST_FUNCTION ix86_libc_has_fast_function -#undef TARGET_GEN_MEMSET_SCRATCH_RTX -#define TARGET_GEN_MEMSET_SCRATCH_RTX ix86_gen_scratch_sse_rtx - #if CHECKING_P #undef TARGET_RUN_TARGET_SELFTESTS #define TARGET_RUN_TARGET_SELFTESTS selftest::ix86_run_selftests diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index c4a92a5ebee..4bb48c5428c 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -12001,13 +12001,6 @@ This function prepares to emit a conditional comparison within a sequence @var{bit_code} is @code{AND} or @code{IOR}, which is the op on the compares. @end deftypefn -@deftypefn {Target Hook} rtx TARGET_GEN_MEMSET_SCRATCH_RTX (machine_mode @var{mode}) -This hook should return an rtx for a scratch register in @var{mode} to -be used when expanding memset calls. The backend can use a hard scratch -register to avoid stack realignment when expanding memset. The default -is @code{gen_reg_rtx}. -@end deftypefn - @deftypefn {Target Hook} unsigned TARGET_LOOP_UNROLL_ADJUST (unsigned @var{nunroll}, class loop *@var{loop}) This target hook returns a new value for the number of times @var{loop} should be unrolled. The parameter @var{nunroll} is the number of times diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 4075e71624c..f7ab5d48a63 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -7787,8 +7787,6 @@ lists. @hook TARGET_GEN_CCMP_NEXT -@hook TARGET_GEN_MEMSET_SCRATCH_RTX - @hook TARGET_LOOP_UNROLL_ADJUST @defmac POWI_MAX_MULTS diff --git a/gcc/target.def b/gcc/target.def index f401fe148ee..1b9c882229e 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -2738,15 +2738,6 @@ DEFHOOK rtx, (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx prev, int cmp_code, tree op0, tree op1, int bit_code), NULL) -DEFHOOK -(gen_memset_scratch_rtx, - "This hook should return an rtx for a scratch register in @var{mode} to\n\ -be used when expanding memset calls. The backend can use a hard scratch\n\ -register to avoid stack realignment when expanding memset. The default\n\ -is @code{gen_reg_rtx}.", - rtx, (machine_mode mode), - gen_reg_rtx) - /* Return a new value for loop unroll size. */ DEFHOOK (loop_unroll_adjust,