diff mbox series

RISC-V: Fix Bug 109092

Message ID 20230313141757.277008-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Fix Bug 109092 |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai March 13, 2023, 2:17 p.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

This patch fix bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092.

gcc/ChangeLog:

        * config/riscv/riscv.md: Fix subreg bug.

---
 gcc/config/riscv/riscv.md | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Jeff Law March 14, 2023, 6:13 p.m. UTC | #1 
On 3/13/23 08:17, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> This patch fix bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/riscv.md: Fix subreg bug.
LGTM.  Do you have write access now?  If so, go ahead and commit this patch.

Do you have any interest in fixing up a similar bug in peephole.md?

Jeff
juzhe.zhong@rivai.ai March 15, 2023, 3:05 a.m. UTC | #2 
Yes, I have write access. However, I am new to commit patch to GCC trunk.
I didn't figure out how to commit patch to GCC trunk.
And I am afraid of producing a potential risk to GCC trunk during stage 4 in GCC 13.

So I am gonna learn to commit codes when GCC 14 is open.
And currently, I let Kito commit patch for me. 


juzhe.zhong@rivai.ai
 
From: Jeff Law
Date: 2023-03-15 02:13
To: juzhe.zhong; gcc-patches
CC: kito.cheng
Subject: Re: [PATCH] RISC-V: Fix Bug 109092
 
 
On 3/13/23 08:17, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> This patch fix bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/riscv.md: Fix subreg bug.
LGTM.  Do you have write access now?  If so, go ahead and commit this patch.
 
Do you have any interest in fixing up a similar bug in peephole.md?
 
Jeff
Kito Cheng March 17, 2023, 9:51 a.m. UTC | #3 
Committed with commit log tweak:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=02880e7803b19c357718abd2f0d567b4a761f318

On Wed, Mar 15, 2023 at 11:06 AM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> Yes, I have write access. However, I am new to commit patch to GCC trunk.
> I didn't figure out how to commit patch to GCC trunk.
> And I am afraid of producing a potential risk to GCC trunk during stage 4 in GCC 13.
>
> So I am gonna learn to commit codes when GCC 14 is open.
> And currently, I let Kito commit patch for me.
>
>
> juzhe.zhong@rivai.ai
>
> From: Jeff Law
> Date: 2023-03-15 02:13
> To: juzhe.zhong; gcc-patches
> CC: kito.cheng
> Subject: Re: [PATCH] RISC-V: Fix Bug 109092
>
>
> On 3/13/23 08:17, juzhe.zhong@rivai.ai wrote:
> > From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> >
> > This patch fix bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109092.
> >
> > gcc/ChangeLog:
> >
> >          * config/riscv/riscv.md: Fix subreg bug.
> LGTM.  Do you have write access now?  If so, go ahead and commit this patch.
>
> Do you have any interest in fixing up a similar bug in peephole.md?
>
> Jeff
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 371d6838c0b..700f3c28bc3 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1364,8 +1364,8 @@ 
 	(zero_extend:DI
 	    (match_operand:SI 1 "nonimmediate_operand" " r,m")))]
   "TARGET_64BIT && !TARGET_ZBA
-   && !(REG_P (operands[1])
-        && REGNO (operands[1]) == VL_REGNUM)"
+   && !(register_operand (operands[1], SImode)
+        && reg_or_subregno (operands[1]) == VL_REGNUM)"
   "@
    #
    lwu\t%0,%1"
@@ -1747,7 +1747,7 @@ 
   "(register_operand (operands[0], SImode)
     || reg_or_0_operand (operands[1], SImode))
     && !(register_operand (operands[1], SImode)
-         && REGNO (operands[1]) == VL_REGNUM)"
+         && reg_or_subregno (operands[1]) == VL_REGNUM)"
   { return riscv_output_move (operands[0], operands[1]); }
   [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore,rdvlenb")
    (set_attr "mode" "SI")