diff mbox series

RISC-V: Refine reduction RA constraint according to RVV ISA

Message ID	20230313090540.335536-1-juzhe.zhong@rivai.ai
State	Unresolved
Headers	Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 562883858436 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong <juzhe.zhong@rivai.ai> Subject: [PATCH] RISC-V: Refine reduction RA constraint according to RVV ISA Date: Mon, 13 Mar 2023 17:05:40 +0800 Message-Id: <20230313090540.335536-1-juzhe.zhong@rivai.ai> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 Precedence: list Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org> X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?=
Series	RISC-V: Refine reduction RA constraint according to RVV ISA \| RISC-V: Refine reduction RA constraint according to RVV ISA

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snail/gcc-patch-check	warning	Git am fail log

Commit Message

juzhe.zhong@rivai.ai March 13, 2023, 9:05 a.m. UTC

  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

According to RVV ISA:
14. Vector Reduction Operations

"The destination vector register can overlap the source operands, including the mask register."

gcc/ChangeLog:

        * config/riscv/vector.md: Refine RA constraint.

---
 gcc/config/riscv/vector.md | 96 +++++++++++++++++++-------------------
 1 file changed, 48 insertions(+), 48 deletions(-)

Comments

Jeff Law March 14, 2023, 6:05 p.m. UTC | #1

On 3/13/23 03:05, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> According to RVV ISA:
> 14. Vector Reduction Operations
> 
> "The destination vector register can overlap the source operands, including the mask register."
> 
> gcc/ChangeLog:
> 
>          * config/riscv/vector.md: Refine RA constraint.
This feels like it ought to wait for gcc-14 as well.

One question though, why even bother with the matching constraint at all 
in these patterns?  ISTM it doesn't really accomplish anything. 
Removing it allows a single alternative to handle all the possibilities.

Jeff

juzhe.zhong@rivai.ai March 14, 2023, 11:10 p.m. UTC | #2

Since according to RVV ISA, "The destination vector register can overlap the source operands, including the mask register."
That means we can have vredsum.vs v0,v8,v9,v0.t. This patch is to refine the constraint to allow this happen that the current RA constraint doesn't allow.
Since you can see "vd" to match  "vm", vd doesn't include mask register (v0). This trivial optimization can allow our RA have 1 more register to allocate.
It's overall beneficial to the RA. 

juzhe.zhong@rivai.ai

From: Jeff Law
Date: 2023-03-15 02:05
To: juzhe.zhong; gcc-patches
CC: kito.cheng
Subject: Re: [PATCH] RISC-V: Refine reduction RA constraint according to RVV ISA

On 3/13/23 03:05, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> According to RVV ISA:
> 14. Vector Reduction Operations
> 
> "The destination vector register can overlap the source operands, including the mask register."
> 
> gcc/ChangeLog:
> 
>          * config/riscv/vector.md: Refine RA constraint.
This feels like it ought to wait for gcc-14 as well.

One question though, why even bother with the matching constraint at all 
in these patterns?  ISTM it doesn't really accomplish anything. 
Removing it allows a single alternative to handle all the possibilities.

Jeff

Jeff Law April 21, 2023, 8:32 p.m. UTC | #3

On 3/13/23 03:05, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> According to RVV ISA:
> 14. Vector Reduction Operations
> 
> "The destination vector register can overlap the source operands, including the mask register."
> 
> gcc/ChangeLog:
> 
>          * config/riscv/vector.md: Refine RA constraint.
OK.  Go ahead and install this on the trunk.

jeff

diff mbox series

Patch

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 4ea74372de5..75336b1a515 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -6259,44 +6259,44 @@ 
 ;; For example, The LMUL = 1 corresponding mode of VNx16QImode is VNx4QImode
 ;; for -march=rv*zve32* wheras VNx8QImode for -march=rv*zve64*
 (define_insn "@pred_reduc_<reduc><mode><vlmul1>"
-  [(set (match_operand:<VLMUL1> 0 "register_operand"          "=vd, vd, vr, vr")
+  [(set (match_operand:<VLMUL1> 0 "register_operand"            "=vr,   vr")
 	(unspec:<VLMUL1>
 	  [(unspec:<VM>
-	     [(match_operand:<VM> 1 "vector_mask_operand"     " vm, vm,Wc1,Wc1")
-	      (match_operand 5 "vector_length_operand"        " rK, rK, rK, rK")
-	      (match_operand 6 "const_int_operand"            "  i,  i,  i,  i")
-	      (match_operand 7 "const_int_operand"            "  i,  i,  i,  i")
+	     [(match_operand:<VM> 1 "vector_mask_operand"     "vmWc1,vmWc1")
+	      (match_operand 5 "vector_length_operand"        "   rK,   rK")
+	      (match_operand 6 "const_int_operand"            "    i,    i")
+	      (match_operand 7 "const_int_operand"            "    i,    i")
 	      (reg:SI VL_REGNUM)
 	      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	   (any_reduc:VI
 	     (vec_duplicate:VI
 	       (vec_select:<VEL>
-	         (match_operand:<VLMUL1> 4 "register_operand" " vr, vr, vr, vr")
+	         (match_operand:<VLMUL1> 4 "register_operand" "   vr,   vr")
 	         (parallel [(const_int 0)])))
-	     (match_operand:VI 3 "register_operand"           " vr, vr, vr, vr"))
-	   (match_operand:<VLMUL1> 2 "vector_merge_operand"   " vu,  0, vu,  0")] UNSPEC_REDUC))]
+	     (match_operand:VI 3 "register_operand"           "   vr,   vr"))
+	   (match_operand:<VLMUL1> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_REDUC))]
   "TARGET_VECTOR && TARGET_MIN_VLEN > 32"
   "vred<reduc>.vs\t%0,%3,%4%p1"
   [(set_attr "type" "vired")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
-  [(set (match_operand:<VLMUL1_ZVE32> 0 "register_operand"          "=vd, vd, vr, vr")
+  [(set (match_operand:<VLMUL1_ZVE32> 0 "register_operand"            "=vr,   vr")
 	(unspec:<VLMUL1_ZVE32>
 	  [(unspec:<VM>
-	     [(match_operand:<VM> 1 "vector_mask_operand"           " vm, vm,Wc1,Wc1")
-	      (match_operand 5 "vector_length_operand"              " rK, rK, rK, rK")
-	      (match_operand 6 "const_int_operand"                  "  i,  i,  i,  i")
-	      (match_operand 7 "const_int_operand"                  "  i,  i,  i,  i")
+	     [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,vmWc1")
+	      (match_operand 5 "vector_length_operand"              "   rK,   rK")
+	      (match_operand 6 "const_int_operand"                  "    i,    i")
+	      (match_operand 7 "const_int_operand"                  "    i,    i")
 	      (reg:SI VL_REGNUM)
 	      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	   (any_reduc:VI_ZVE32
 	     (vec_duplicate:VI_ZVE32
 	       (vec_select:<VEL>
-	         (match_operand:<VLMUL1_ZVE32> 4 "register_operand" " vr, vr, vr, vr")
+	         (match_operand:<VLMUL1_ZVE32> 4 "register_operand" "   vr,   vr")
 	         (parallel [(const_int 0)])))
-	     (match_operand:VI_ZVE32 3 "register_operand"           " vr, vr, vr, vr"))
-	   (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand"   " vu,  0, vu,  0")] UNSPEC_REDUC))]
+	     (match_operand:VI_ZVE32 3 "register_operand"           "   vr,   vr"))
+	   (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_REDUC))]
   "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
   "vred<reduc>.vs\t%0,%3,%4%p1"
   [(set_attr "type" "vired")
@@ -6339,90 +6339,90 @@ 
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_reduc_<reduc><mode><vlmul1>"
-  [(set (match_operand:<VLMUL1> 0 "register_operand"          "=vd, vd, vr, vr")
+  [(set (match_operand:<VLMUL1> 0 "register_operand"             "=vr,   vr")
 	(unspec:<VLMUL1>
 	  [(unspec:<VM>
-	     [(match_operand:<VM> 1 "vector_mask_operand"      " vm, vm,Wc1,Wc1")
-	      (match_operand 5 "vector_length_operand"         " rK, rK, rK, rK")
-	      (match_operand 6 "const_int_operand"             "  i,  i,  i,  i")
-	      (match_operand 7 "const_int_operand"             "  i,  i,  i,  i")
+	     [(match_operand:<VM> 1 "vector_mask_operand"      "vmWc1,vmWc1")
+	      (match_operand 5 "vector_length_operand"         "   rK,   rK")
+	      (match_operand 6 "const_int_operand"             "    i,    i")
+	      (match_operand 7 "const_int_operand"             "    i,    i")
 	      (reg:SI VL_REGNUM)
 	      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	   (any_freduc:VF
 	     (vec_duplicate:VF
 	       (vec_select:<VEL>
-	         (match_operand:<VLMUL1> 4 "register_operand" " vr, vr, vr, vr")
+	         (match_operand:<VLMUL1> 4 "register_operand" "   vr,   vr")
 	         (parallel [(const_int 0)])))
-	     (match_operand:VF 3 "register_operand"           " vr, vr, vr, vr"))
-	   (match_operand:<VLMUL1> 2 "vector_merge_operand"   " vu,  0, vu,  0")] UNSPEC_REDUC))]
+	     (match_operand:VF 3 "register_operand"           "   vr,   vr"))
+	   (match_operand:<VLMUL1> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_REDUC))]
   "TARGET_VECTOR && TARGET_MIN_VLEN > 32"
   "vfred<reduc>.vs\t%0,%3,%4%p1"
   [(set_attr "type" "vfredu")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_reduc_<reduc><mode><vlmul1_zve32>"
-  [(set (match_operand:<VLMUL1_ZVE32> 0 "register_operand"          "=vd, vd, vr, vr")
+  [(set (match_operand:<VLMUL1_ZVE32> 0 "register_operand"            "=vr,   vr")
 	(unspec:<VLMUL1_ZVE32>
 	  [(unspec:<VM>
-	     [(match_operand:<VM> 1 "vector_mask_operand"           " vm, vm,Wc1,Wc1")
-	      (match_operand 5 "vector_length_operand"              " rK, rK, rK, rK")
-	      (match_operand 6 "const_int_operand"                  "  i,  i,  i,  i")
-	      (match_operand 7 "const_int_operand"                  "  i,  i,  i,  i")
+	     [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,vmWc1")
+	      (match_operand 5 "vector_length_operand"              "   rK,   rK")
+	      (match_operand 6 "const_int_operand"                  "    i,    i")
+	      (match_operand 7 "const_int_operand"                  "    i,    i")
 	      (reg:SI VL_REGNUM)
 	      (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	   (any_freduc:VF_ZVE32
 	     (vec_duplicate:VF_ZVE32
 	       (vec_select:<VEL>
-	         (match_operand:<VLMUL1_ZVE32> 4 "register_operand" " vr, vr, vr, vr")
+	         (match_operand:<VLMUL1_ZVE32> 4 "register_operand" "   vr,   vr")
 	         (parallel [(const_int 0)])))
-	     (match_operand:VF_ZVE32 3 "register_operand"           " vr, vr, vr, vr"))
-	   (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand"   " vu,  0, vu,  0")] UNSPEC_REDUC))]
+	     (match_operand:VF_ZVE32 3 "register_operand"           "   vr,   vr"))
+	   (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_REDUC))]
   "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
   "vfred<reduc>.vs\t%0,%3,%4%p1"
   [(set_attr "type" "vfredu")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_reduc_plus<order><mode><vlmul1>"
-  [(set (match_operand:<VLMUL1> 0 "register_operand"             "=vd, vd, vr, vr")
+  [(set (match_operand:<VLMUL1> 0 "register_operand"               "=vr,   vr")
 	(unspec:<VLMUL1>
 	  [(unspec:<VLMUL1>
 	    [(unspec:<VM>
-	       [(match_operand:<VM> 1 "vector_mask_operand"      " vm, vm,Wc1,Wc1")
-	        (match_operand 5 "vector_length_operand"         " rK, rK, rK, rK")
-	        (match_operand 6 "const_int_operand"             "  i,  i,  i,  i")
-	        (match_operand 7 "const_int_operand"             "  i,  i,  i,  i")
+	       [(match_operand:<VM> 1 "vector_mask_operand"      "vmWc1,vmWc1")
+	        (match_operand 5 "vector_length_operand"         "   rK,   rK")
+	        (match_operand 6 "const_int_operand"             "    i,    i")
+	        (match_operand 7 "const_int_operand"             "    i,    i")
 	        (reg:SI VL_REGNUM)
 	        (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	     (plus:VF
 	       (vec_duplicate:VF
 	         (vec_select:<VEL>
-	           (match_operand:<VLMUL1> 4 "register_operand" " vr, vr, vr, vr")
+	           (match_operand:<VLMUL1> 4 "register_operand" "   vr,   vr")
 	           (parallel [(const_int 0)])))
-	       (match_operand:VF 3 "register_operand"           " vr, vr, vr, vr"))
-	     (match_operand:<VLMUL1> 2 "vector_merge_operand"   " vu,  0, vu,  0")] UNSPEC_REDUC)] ORDER))]
+	       (match_operand:VF 3 "register_operand"           "   vr,   vr"))
+	     (match_operand:<VLMUL1> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_REDUC)] ORDER))]
   "TARGET_VECTOR && TARGET_MIN_VLEN > 32"
   "vfred<order>sum.vs\t%0,%3,%4%p1"
   [(set_attr "type" "vfred<order>")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "@pred_reduc_plus<order><mode><vlmul1_zve32>"
-  [(set (match_operand:<VLMUL1_ZVE32> 0 "register_operand"            "=vd, vd, vr, vr")
+  [(set (match_operand:<VLMUL1_ZVE32> 0 "register_operand"              "=vr,   vr")
 	(unspec:<VLMUL1_ZVE32>
 	  [(unspec:<VLMUL1_ZVE32>
 	    [(unspec:<VM>
-	       [(match_operand:<VM> 1 "vector_mask_operand"           " vm, vm,Wc1,Wc1")
-	        (match_operand 5 "vector_length_operand"              " rK, rK, rK, rK")
-	        (match_operand 6 "const_int_operand"                  "  i,  i,  i,  i")
-	        (match_operand 7 "const_int_operand"                  "  i,  i,  i,  i")
+	       [(match_operand:<VM> 1 "vector_mask_operand"           "vmWc1,vmWc1")
+	        (match_operand 5 "vector_length_operand"              "   rK,   rK")
+	        (match_operand 6 "const_int_operand"                  "    i,    i")
+	        (match_operand 7 "const_int_operand"                  "    i,    i")
 	        (reg:SI VL_REGNUM)
 	        (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	     (plus:VF_ZVE32
 	       (vec_duplicate:VF_ZVE32
 	         (vec_select:<VEL>
-	           (match_operand:<VLMUL1_ZVE32> 4 "register_operand" " vr, vr, vr, vr")
+	           (match_operand:<VLMUL1_ZVE32> 4 "register_operand" "   vr,   vr")
 	           (parallel [(const_int 0)])))
-	       (match_operand:VF_ZVE32 3 "register_operand"           " vr, vr, vr, vr"))
-	     (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand"   " vu,  0, vu,  0")] UNSPEC_REDUC)] ORDER))]
+	       (match_operand:VF_ZVE32 3 "register_operand"           "   vr,   vr"))
+	     (match_operand:<VLMUL1_ZVE32> 2 "vector_merge_operand"   "   vu,    0")] UNSPEC_REDUC)] ORDER))]
   "TARGET_VECTOR && TARGET_MIN_VLEN == 32"
   "vfred<order>sum.vs\t%0,%3,%4%p1"
   [(set_attr "type" "vfred<order>")