From patchwork Fri Mar 10 17:51:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Pinski X-Patchwork-Id: 67618 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp1013026wrd; Fri, 10 Mar 2023 09:52:07 -0800 (PST) X-Google-Smtp-Source: AK7set8LkKkhii6ICAMBPJHkVLSpuNe99abRpMRDbWD6STdrytTYB3vbgi8/8dQTSZ/FEgoWylHk X-Received: by 2002:a17:906:5fd3:b0:8a4:e2aa:6cd9 with SMTP id k19-20020a1709065fd300b008a4e2aa6cd9mr23613837ejv.19.1678470727308; Fri, 10 Mar 2023 09:52:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678470727; cv=none; d=google.com; s=arc-20160816; b=q3hU2+f2OdQz/TDqRGQGp4btmVGufjUh3wDUshEa4pscK0yCFQHCvX75jnlUhRW7G5 keDbfGAgtVNFL+hQFVX8o7w94qWcQUsPuliZF1NCGtPgT8nnMQrwBvjAl/lY1bCCqVYN wsogRgVll+FReNWC7GNrG7/HY8T/eEkGyuDAzK8lP0WJd9K+unBupoFE+wTdfDgM5FwC uoRQ5m0ycqKhE6aIz9P1D56OxvjWeXIrkxu7cGFiuKSRhkh4zOrXjwZu+IYdGsQyybZz ip/6bZg0n+S+PSsPTzo88n8udWd28n0/E2TyrYak4lvNs3ZJ1ZmfHiu+W2JKiSpBXs+F eJZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=Ynqp4sjR+V02nXnd73l7bjA4N7nT0UWDm2CCl29dRFM=; b=IOKUq8DLzVmtt4i4LAdX6/Fdlt0OCkTgDZb5KqwQDErz/5gFkKvhxdKb6nKuRNnOpD Zryr9Y0hjfOJcMDjn0DDnAUag8zlcrZNbI6gGyViHg8NRYR9PuHpuTaz2w8cy73nbVIO 6NSP04fSh2m6kycIQ9dZ3znR6r3PRF2M+OSnoD3tnDF0T3vjrsoQ27F7cewovkqyOciq B6AISqRyAchGnv+UacNHNv5P0A5t2HL3eXMlvsM/RBboFcZeU7ty98nbkKbW2WJyH0Sp equYO+HjEPhBEhTvuw3vtgBPoDnpbAVI/6bYOMVTHv1Om+/+Fhy03VdX2JJcw/xr31Z7 U7pQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="kna/6KY6"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id q25-20020a056402033900b004c3d955605fsi554606edw.631.2023.03.10.09.52.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Mar 2023 09:52:07 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b="kna/6KY6"; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AF3F23857C71 for ; Fri, 10 Mar 2023 17:52:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AF3F23857C71 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1678470721; bh=Ynqp4sjR+V02nXnd73l7bjA4N7nT0UWDm2CCl29dRFM=; h=To:CC:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=kna/6KY6uGnWSGRuYAY91Ofx9SXC4dCPwDBcS0nIFt4jZpTm6ZxTSeYnsFOwEQEBZ NMONiN2ZVnt3oOmrmbHfMkwnoMbJjFyqmQZIkle2Yk+Mqbbro4Qex083pRg44r1Q09 ZFVpdzacyhbBnrEBBPMgoBhBU7O/thz4//aBXyUQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by sourceware.org (Postfix) with ESMTPS id C3D193858D32 for ; Fri, 10 Mar 2023 17:51:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C3D193858D32 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32AG3VP7009096 for ; Fri, 10 Mar 2023 09:51:16 -0800 Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3p80k7ass9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 10 Mar 2023 09:51:16 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 10 Mar 2023 09:51:13 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 10 Mar 2023 09:51:13 -0800 Received: from vpnclient.wrightpinski.org.com (unknown [10.76.242.80]) by maili.marvell.com (Postfix) with ESMTP id 42AF05B693D; Fri, 10 Mar 2023 09:51:13 -0800 (PST) To: CC: Andrew Pinski Subject: [COMMITTED] Fix PR 108874: aarch64 code regression with shift and ands Date: Fri, 10 Mar 2023 09:51:02 -0800 Message-ID: <20230310175102.2937497-1-apinski@marvell.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Proofpoint-GUID: KGR2TN5gGIzuxcuDhzZ84GySvLDrU7nQ X-Proofpoint-ORIG-GUID: KGR2TN5gGIzuxcuDhzZ84GySvLDrU7nQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-10_08,2023-03-10_01,2023-02-09_01 X-Spam-Status: No, score=-14.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrew Pinski via Gcc-patches From: Andrew Pinski Reply-To: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759959393298352667?= X-GMAIL-MSGID: =?utf-8?q?1760004121316023629?= After r6-2044-g98e30e515f184b, code like "((x & 0xff00ff00U) >> 8)" would be optimized like (x >> 8) & 0xff00ffU which is normally better except on aarch64, the shift right could be combined with another operation in some cases. So we need to add a few define_splits to the aarch64 backends that match "((x >> shift) & CST0) OP Y" and splits it to: TMP = X & CST1 (TMP >> shift) OP Y Note this also gets us to matching rev16 back too so I added a testcase to make sure we don't lose that matching any more. Note when the generic patch to recognize those as bswap ROT 16, we might regress again and need to add a few more patterns to the aarch64 backend but will deal with that once that happens. Committed as approved after a bootstrapp/test on aarch64-linux-gnu with no regressions. gcc/ChangeLog: * config/aarch64/aarch64.md: Add a new define_split to help combine. gcc/testsuite/ChangeLog: * gcc.target/aarch64/rev16_2.c: New test. * gcc.target/aarch64/shift_and_operator-1.c: New test. --- gcc/config/aarch64/aarch64.md | 23 +++++++++++ gcc/testsuite/gcc.target/aarch64/rev16_2.c | 39 +++++++++++++++++++ .../gcc.target/aarch64/shift_and_operator-1.c | 22 +++++++++++ 3 files changed, 84 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/rev16_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/shift_and_operator-1.c diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index af9087508ac..022eef80bc1 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4656,6 +4656,29 @@ (define_insn "*_3" [(set_attr "type" "logic_shift_imm")] ) +(define_split + [(set (match_operand:GPI 0 "register_operand") + (LOGICAL_OR_PLUS:GPI + (and:GPI + (lshiftrt:GPI (match_operand:GPI 1 "register_operand") + (match_operand:QI 2 "aarch64_shift_imm_")) + (match_operand:GPI 3 "aarch64_logical_immediate")) + (match_operand:GPI 4 "register_operand")))] + "can_create_pseudo_p () + && aarch64_bitmask_imm (UINTVAL (operands[3]) << UINTVAL (operands[2]), + mode)" + [(set (match_dup 5) (and:GPI (match_dup 1) (match_dup 6))) + (set (match_dup 0) (LOGICAL_OR_PLUS:GPI + (lshiftrt:GPI (match_dup 5) (match_dup 2)) + (match_dup 4)))] + { + operands[5] = gen_reg_rtx (mode); + operands[6] + = gen_int_mode (UINTVAL (operands[3]) << UINTVAL (operands[2]), + mode); + } +) + (define_split [(set (match_operand:GPI 0 "register_operand") (LOGICAL_OR_PLUS:GPI diff --git a/gcc/testsuite/gcc.target/aarch64/rev16_2.c b/gcc/testsuite/gcc.target/aarch64/rev16_2.c new file mode 100644 index 00000000000..621eb5dfbf0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/rev16_2.c @@ -0,0 +1,39 @@ +/* { dg-options "-O2" } */ +/* { dg-do compile } */ + +extern void abort (void); + +typedef unsigned int __u32; + +__u32 +__rev16_32_alt (__u32 x) +{ + return (((__u32)(x) & (__u32)0xff00ff00UL) >> 8) + | (((__u32)(x) & (__u32)0x00ff00ffUL) << 8); +} + +__u32 +__rev16_32 (__u32 x) +{ + return (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) + | (((__u32)(x) & (__u32)0xff00ff00UL) >> 8); +} + +typedef unsigned long long __u64; + +__u64 +__rev16_64_alt (__u64 x) +{ + return (((__u64)(x) & (__u64)0xff00ff00ff00ff00UL) >> 8) + | (((__u64)(x) & (__u64)0x00ff00ff00ff00ffUL) << 8); +} + +__u64 +__rev16_64 (__u64 x) +{ + return (((__u64)(x) & (__u64)0x00ff00ff00ff00ffUL) << 8) + | (((__u64)(x) & (__u64)0xff00ff00ff00ff00UL) >> 8); +} + +/* { dg-final { scan-assembler-times "rev16\\tx\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-times "rev16\\tw\[0-9\]+" 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/shift_and_operator-1.c b/gcc/testsuite/gcc.target/aarch64/shift_and_operator-1.c new file mode 100644 index 00000000000..49152c5495a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/shift_and_operator-1.c @@ -0,0 +1,22 @@ +/* { dg-options "-O2" } */ +/* { dg-do compile } */ + +unsigned f(unsigned x, unsigned b) +{ + return ((x & 0xff00ff00U) >> 8) | b; +} + +unsigned f0(unsigned x, unsigned b) +{ + return ((x & 0xff00ff00U) >> 8) ^ b; +} +unsigned f1(unsigned x, unsigned b) +{ + return ((x & 0xff00ff00U) >> 8) + b; +} + +/* { dg-final { scan-assembler-times "lsr\\tw\[0-9\]+" 0 } } */ +/* { dg-final { scan-assembler-times "lsr 8" 3 } } */ +/* { dg-final { scan-assembler-times "eor\\tw\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "add\\tw\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "orr\\tw\[0-9\]+" 1 } } */