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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id y7-20020a056402134700b004bff4ce5ec3si1907418edw.371.2023.03.10.00.09.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Mar 2023 00:09:39 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 53445385B520 for ; Fri, 10 Mar 2023 08:09:36 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id C444F3858C54 for ; Fri, 10 Mar 2023 08:09:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C444F3858C54 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp64t1678435744twy7ufqk Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 10 Mar 2023 16:09:03 +0800 (CST) X-QQ-SSF: 01400000000000E0N000000A0000000 X-QQ-FEAT: QityeSR92A3kzfQs2jfecrS3rrPd9agB3BLpO7h1sfBBoKMxgHrV6ynUpegnA 4DLzS++X8HX9eEpoSqoRTyXRx/xYBhLMZbSd0rmlH7I/IvmbyE/oUOOBGeQ3FjOqDCAlzSV RRAoED2z2wTq3oa8Z5XdUrPK28ApEwsvOsYjdmxDTo3/TgVEHzKClZQR7RCiOnfOMpPn+AI l0v6Wdcm9bZJMwJKt1YXR7t+C2h8ZJYQensktT/rx/eeZApe+ANUjx5LuOiUDUnaMiUEKc9 q5OABnRBOTgCw3MnfV/Omx4P5mPgfSZctzve1UO8phHPBy1W8f/fJtCTUctPigxqs8yhzPp Z+0V4uhFjq+R11M5tU73mY8DaVhulkUZFDIQB6K6HpWOZK8L8+Zd1ewc5C4DAfxCObg7cEC X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Fix ICE of RVV compare intrinsic Date: Fri, 10 Mar 2023 16:08:57 +0800 Message-Id: <20230310080857.186586-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, WEIRD_PORT autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759967476356277021?= X-GMAIL-MSGID: =?utf-8?q?1759967476356277021?= From: Ju-Zhe Zhong vfrsub_vf_m.cpp: In function 'int main()': vfrsub_vf_m.cpp:5:43: error: invalid argument to built-in function 5 | vbool32_t d = __riscv_vmflt_vf_f32m1_b32(c, b, 8); | ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~ during RTL pass: expand vfrsub_vf_m.cpp:5:43: internal compiler error: Segmentation fault 0x19f1b89 crash_signal ../../../../riscv-gnu-toolchain-trunk/riscv-gcc/gcc/toplev.cc:314 0x1472e2f store_expr(tree_node*, rtx_def*, int, bool, bool) ../../../../riscv-gnu-toolchain-trunk/riscv-gcc/gcc/expr.cc:6348 gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (function_expander::use_compare_insn): Add operand predicate check. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/bug-1.c: New test. --- gcc/config/riscv/riscv-vector-builtins.cc | 9 +++ .../gcc.target/riscv/rvv/base/bug-1.c | 79 +++++++++++++++++++ 2 files changed, 88 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-1.c diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index fcda3863576..75e65091db3 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -3084,6 +3084,15 @@ function_expander::use_compare_insn (rtx_code rcode, insn_code icode) rtx op1 = expand_normal (CALL_EXPR_ARG (exp, arg_offset++)); rtx op2 = expand_normal (CALL_EXPR_ARG (exp, arg_offset++)); + if (!insn_operand_matches (icode, opno + 1, op1)) + op1 = force_reg (mode, op1); + if (!insn_operand_matches (icode, opno + 2, op2)) + { + if (VECTOR_MODE_P (GET_MODE (op2))) + op2 = force_reg (mode, op2); + else + op2 = force_reg (GET_MODE_INNER (mode), op2); + } rtx comparison = gen_rtx_fmt_ee (rcode, mask_mode, op1, op2); if (!VECTOR_MODE_P (GET_MODE (op2))) comparison = gen_rtx_fmt_ee (rcode, mask_mode, op1, diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-1.c new file mode 100644 index 00000000000..a8843674e31 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-1.c @@ -0,0 +1,79 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O0" } */ + +#include "riscv_vector.h" + +int +f0 () +{ + float b; + vfloat32m1_t c; + vbool32_t d = __riscv_vmflt_vf_f32m1_b32 (c, b, 8); + return 0; +} + +int +f1 () +{ + vfloat32m1_t c; + vbool32_t d = __riscv_vmflt_vf_f32m1_b32 (c, 0, 8); + return 0; +} + +int +f2 () +{ + vfloat32m1_t c; + vbool32_t d = __riscv_vmflt_vf_f32m1_b32 (c, 55.55, 8); + return 0; +} + +int +f3 () +{ + int32_t b; + vint32m1_t c; + vbool32_t d = __riscv_vmseq_vx_i32m1_b32 (c, b, 8); + return 0; +} + +int +f4 () +{ + vint32m1_t c; + vbool32_t d = __riscv_vmseq_vx_i32m1_b32 (c, 11, 8); + return 0; +} + +int +f5 () +{ + int64_t b; + vint64m1_t c; + vbool64_t d = __riscv_vmseq_vx_i64m1_b64 (c, b, 8); + return 0; +} + +int +f6 () +{ + vint64m1_t c; + vbool64_t d = __riscv_vmseq_vx_i64m1_b64 (c, 11, 8); + return 0; +} + +int +f7 () +{ + vint64m1_t c; + vbool64_t d = __riscv_vmseq_vx_i64m1_b64 (c, 0xAAAA, 8); + return 0; +} + +int +f8 () +{ + vint64m1_t c; + vbool64_t d = __riscv_vmseq_vx_i64m1_b64 (c, 0xAAAAAAAAAAAAAA, 8); + return 0; +}