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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id o27-20020a1709061d5b00b008e161646775si970684ejh.180.2023.03.09.22.01.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 22:01:11 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=wJ4jYkJG; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 61AC83858416 for ; Fri, 10 Mar 2023 06:01:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 61AC83858416 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1678428068; bh=vmLzYvgPQPUqKizoAXJ2H+BHlEg/7y1egimYidmx0zg=; h=To:CC:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=wJ4jYkJGS/h7QcvCk3RadJCTeihqhd4LieL6+XzQsILAYKjEzP0D/ulT1SXtrg45H 4/+rjchCm1CFFwtuP33whR9JnFNnUY6WNP8YqBgWBQi9mWAGo++e1HFQ0shL+FMYho 5pbp91OiFipgtHuYm2nhshCntnBUxHl3jhUGfWoM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id 9958F3858C5E for ; Fri, 10 Mar 2023 06:00:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9958F3858C5E Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32A5bsok025800 for ; Thu, 9 Mar 2023 22:00:24 -0800 Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3p7n7dhnes-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 09 Mar 2023 22:00:24 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 9 Mar 2023 22:00:22 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Thu, 9 Mar 2023 22:00:22 -0800 Received: from vpnclient.wrightpinski.org.com (unknown [10.69.242.67]) by maili.marvell.com (Postfix) with ESMTP id C7BAD5C68E6; Thu, 9 Mar 2023 22:00:16 -0800 (PST) To: CC: Andrew Pinski Subject: [PATCH] Fix PR 108874: aarch64 code regression with shift and ands Date: Thu, 9 Mar 2023 21:59:47 -0800 Message-ID: <20230310055947.2918320-1-apinski@marvell.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Proofpoint-GUID: f36KTyZEyuHXPDf1ER_VSuIU63iNeUYv X-Proofpoint-ORIG-GUID: f36KTyZEyuHXPDf1ER_VSuIU63iNeUYv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-10_02,2023-03-09_01,2023-02-09_01 X-Spam-Status: No, score=-14.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrew Pinski via Gcc-patches From: Andrew Pinski Reply-To: Andrew Pinski Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759959393298352667?= X-GMAIL-MSGID: =?utf-8?q?1759959393298352667?= After r6-2044-g98e30e515f184b, code like "((x & 0xff00ff00U) >> 8)" would be optimized like (x >> 8) & 0xff00ffU which is normally better except on aarch64, the shift right could be combined with another operation in some cases. So we need to add a few define_splits to the aarch64 backends that match "((x >> shift) & CST0) OP Y" and splits it to: TMP = X & CST1 (TMP >> shift) OP Y Note this also gets us to matching rev16 back too so I added a testcase to make sure we don't lose that matching any more. Note when the generic patch to recognize those as bswap ROT 16, we might regress again and need to add a few more patterns to the aarch64 backend but will deal with that once that happens. OK? Bootstrapped and tested on aarch64 with no regressions. gcc/ChangeLog: * config/aarch64/aarch64.md: Add a new define_split to help combine. gcc/testsuite/ChangeLog: * gcc.target/aarch64/rev16_2.c: New test. * gcc.target/aarch64/shift_and_operator-1.c: New test. --- gcc/config/aarch64/aarch64.md | 21 ++++++++++ gcc/testsuite/gcc.target/aarch64/rev16_2.c | 39 +++++++++++++++++++ .../gcc.target/aarch64/shift_and_operator-1.c | 22 +++++++++++ 3 files changed, 82 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/rev16_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/shift_and_operator-1.c diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index af9087508ac..41cc563f10c 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4656,6 +4656,27 @@ (define_insn "*_3" [(set_attr "type" "logic_shift_imm")] ) +(define_split + [(set (match_operand:GPI 0 "register_operand") + (LOGICAL_OR_PLUS:GPI + (and:GPI + (lshiftrt:GPI (match_operand:GPI 1 "register_operand") + (match_operand:QI 2 "aarch64_shift_imm_")) + (match_operand:GPI 3 "aarch64_logical_immediate")) + (match_operand:GPI 4 "register_operand")))] + "can_create_pseudo_p () + && aarch64_bitmask_imm (UINTVAL (operands[3]) << UINTVAL (operands[2]), mode)" + [(set (match_dup 5) (and:GPI (match_dup 1) (match_dup 6))) + (set (match_dup 0) (match_dup 7))] + { + operands[5] = gen_reg_rtx (mode); + operands[6] = gen_int_mode (UINTVAL (operands[3]) << UINTVAL (operands[2]), mode); + rtx shift = gen_rtx_LSHIFTRT (mode, operands[5], operands[2]); + rtx_code new_code = ; + operands[7] = gen_rtx_fmt_ee (new_code, mode, shift, operands[4]); + } +) + (define_split [(set (match_operand:GPI 0 "register_operand") (LOGICAL_OR_PLUS:GPI diff --git a/gcc/testsuite/gcc.target/aarch64/rev16_2.c b/gcc/testsuite/gcc.target/aarch64/rev16_2.c new file mode 100644 index 00000000000..621eb5dfbf0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/rev16_2.c @@ -0,0 +1,39 @@ +/* { dg-options "-O2" } */ +/* { dg-do compile } */ + +extern void abort (void); + +typedef unsigned int __u32; + +__u32 +__rev16_32_alt (__u32 x) +{ + return (((__u32)(x) & (__u32)0xff00ff00UL) >> 8) + | (((__u32)(x) & (__u32)0x00ff00ffUL) << 8); +} + +__u32 +__rev16_32 (__u32 x) +{ + return (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) + | (((__u32)(x) & (__u32)0xff00ff00UL) >> 8); +} + +typedef unsigned long long __u64; + +__u64 +__rev16_64_alt (__u64 x) +{ + return (((__u64)(x) & (__u64)0xff00ff00ff00ff00UL) >> 8) + | (((__u64)(x) & (__u64)0x00ff00ff00ff00ffUL) << 8); +} + +__u64 +__rev16_64 (__u64 x) +{ + return (((__u64)(x) & (__u64)0x00ff00ff00ff00ffUL) << 8) + | (((__u64)(x) & (__u64)0xff00ff00ff00ff00UL) >> 8); +} + +/* { dg-final { scan-assembler-times "rev16\\tx\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-times "rev16\\tw\[0-9\]+" 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/shift_and_operator-1.c b/gcc/testsuite/gcc.target/aarch64/shift_and_operator-1.c new file mode 100644 index 00000000000..49152c5495a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/shift_and_operator-1.c @@ -0,0 +1,22 @@ +/* { dg-options "-O2" } */ +/* { dg-do compile } */ + +unsigned f(unsigned x, unsigned b) +{ + return ((x & 0xff00ff00U) >> 8) | b; +} + +unsigned f0(unsigned x, unsigned b) +{ + return ((x & 0xff00ff00U) >> 8) ^ b; +} +unsigned f1(unsigned x, unsigned b) +{ + return ((x & 0xff00ff00U) >> 8) + b; +} + +/* { dg-final { scan-assembler-times "lsr\\tw\[0-9\]+" 0 } } */ +/* { dg-final { scan-assembler-times "lsr 8" 3 } } */ +/* { dg-final { scan-assembler-times "eor\\tw\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "add\\tw\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "orr\\tw\[0-9\]+" 1 } } */