diff mbox series

RISC-V: Fix ICE for avl_single-86/avl_single-88/avl_single-90

Message ID 20230305102430.266375-1-juzhe.zhong@rivai.ai
State Unresolved
Headers
Series RISC-V: Fix ICE for avl_single-86/avl_single-88/avl_single-90 |

Checks

Context Check Description
snail/gcc-patch-check warning Git am fail log

Commit Message

juzhe.zhong@rivai.ai March 5, 2023, 10:24 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-86.c  -Og -g  (internal
compiler error: Segmentation fault)
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-86.c  -Og -g  (test for
excess errors)
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-88.c  -Og -g  (internal
compiler error: Segmentation fault)
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-88.c  -Og -g  (test for
excess errors)
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-90.c  -Og -g  (internal
compiler error: Segmentation fault)
FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-90.c  -Og -g  (test for
excess errors)

gcc/ChangeLog:

        * config/riscv/riscv-vsetvl.cc (reg_available_p): Fix bug.
        (pass_vsetvl::backward_demand_fusion): Ditto.

---
 gcc/config/riscv/riscv-vsetvl.cc | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

Comments

Kito Cheng March 5, 2023, 5:24 p.m. UTC | #1 
Committed, thanks for the fix :)

On Sun, Mar 5, 2023 at 6:25 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-86.c  -Og -g  (internal
> compiler error: Segmentation fault)
> FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-86.c  -Og -g  (test for
> excess errors)
> FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-88.c  -Og -g  (internal
> compiler error: Segmentation fault)
> FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-88.c  -Og -g  (test for
> excess errors)
> FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-90.c  -Og -g  (internal
> compiler error: Segmentation fault)
> FAIL: gcc.target/riscv/rvv/vsetvl/avl_single-90.c  -Og -g  (test for
> excess errors)
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-vsetvl.cc (reg_available_p): Fix bug.
>         (pass_vsetvl::backward_demand_fusion): Ditto.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
> index 9e25102a4f2..73f36a70331 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -1528,7 +1528,7 @@ static bool
>  reg_available_p (const bb_info *bb, const vector_insn_info &info)
>  {
>    if (!info.get_avl_source ())
> -    return true;
> +    return false;
>    insn_info *insn = info.get_avl_source ()->insn ();
>    if (insn->bb () == bb)
>      return before_p (insn, info.get_insn ());
> @@ -3040,6 +3040,12 @@ pass_vsetvl::backward_demand_fusion (void)
>             continue;
>           if (e->src->index == ENTRY_BLOCK_PTR_FOR_FN (cfun)->index)
>             continue;
> +         /* If prop is demand of vsetvl instruction and reaching doesn't demand
> +            AVL. We don't backward propagate since vsetvl instruction has no
> +            side effects.  */
> +         if (vsetvl_insn_p (prop.get_insn ()->rtl ())
> +             && propagate_avl_across_demands_p (prop, block_info.reaching_out))
> +           continue;
>
>           if (block_info.reaching_out.unknown_p ())
>             continue;
> --
> 2.36.3
>
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 9e25102a4f2..73f36a70331 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1528,7 +1528,7 @@  static bool
 reg_available_p (const bb_info *bb, const vector_insn_info &info)
 {
   if (!info.get_avl_source ())
-    return true;
+    return false;
   insn_info *insn = info.get_avl_source ()->insn ();
   if (insn->bb () == bb)
     return before_p (insn, info.get_insn ());
@@ -3040,6 +3040,12 @@  pass_vsetvl::backward_demand_fusion (void)
 	    continue;
 	  if (e->src->index == ENTRY_BLOCK_PTR_FOR_FN (cfun)->index)
 	    continue;
+	  /* If prop is demand of vsetvl instruction and reaching doesn't demand
+	     AVL. We don't backward propagate since vsetvl instruction has no
+	     side effects.  */
+	  if (vsetvl_insn_p (prop.get_insn ()->rtl ())
+	      && propagate_avl_across_demands_p (prop, block_info.reaching_out))
+	    continue;
 
 	  if (block_info.reaching_out.unknown_p ())
 	    continue;