@@ -3093,4 +3093,5 @@ (define_insn "riscv_prefetchi_<mode>"
(include "pic.md")
(include "generic.md")
(include "sifive-7.md")
+(include "thead.md")
(include "vector.md")
new file mode 100644
@@ -0,0 +1,31 @@
+;; Machine description for T-Head vendor extensions
+;; Copyright (C) 2021-2022 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+;; XTheadBa
+
+(define_insn "*th_addsl<mode>4"
+ [(set (match_operand:X 0 "register_operand" "=r")
+ (plus:X (ashift:X (match_operand:X 1 "register_operand" "r")
+ (match_operand 2 "const_int_operand" "n"))
+ (match_operand:X 3 "register_operand" "r")))]
+ "TARGET_XTHEADBA
+ && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)"
+ "th.addsl\t%0,%3,%1,%2"
+ [(set_attr "type" "bitmanip")
+ (set_attr "mode" "<X:MODE>")])
new file mode 100644
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadba" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadba" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+long
+test_1 (long a, long b)
+{
+ /* th.addsl aX, aX, 1 */
+ return a + (b << 1);
+}
+
+int
+foos (short *x, int n)
+{
+ /* th.addsl aX, aX, 1 */
+ return x[n];
+}
+
+long
+test_2 (long a, long b)
+{
+ /* th.addsl aX, aX, 2 */
+ return a + (b << 2);
+}
+
+int
+fooi (int *x, int n)
+{
+ /* th.addsl aX, aX, 2 */
+ return x[n];
+}
+
+long
+test_3 (long a, long b)
+{
+ /* th.addsl aX, aX, 3 */
+ return a + (b << 3);
+}
+
+long
+fool (long *x, int n)
+{
+ /* th.addsl aX, aX, 2 (rv32) */
+ /* th.addsl aX, aX, 3 (rv64) */
+ return x[n];
+}
+
+/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,1" 2 } } */
+
+/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 3 { target { rv32 } } } } */
+/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 2 { target { rv64 } } } } */
+
+/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 1 { target { rv32 } } } } */
+/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 2 { target { rv64 } } } } */