diff mbox series

MIPS: Account for LWL/LWR in store_by_pieces_p.

Message ID 20230221031524.220339-1-xin.liu@oss.cipunited.com
State Accepted
Headers
Series MIPS: Account for LWL/LWR in store_by_pieces_p. |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Xin Liu Feb. 21, 2023, 3:16 a.m. UTC 
  From: Matthew Fortune <matthew.fortune@imgtec.com>

---
 gcc/config/mips/mips.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 590c311e98c..bb9f4e19c22 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -8853,7 +8853,7 @@  mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
 	  LW/SWL/SWR sequence.  This is often better than the 4 LIs and
 	  4 SBs that we would generate when storing by pieces.  */
   if (align <= BITS_PER_UNIT)
-    return size < 4;
+    return size < 4 || !ISA_HAS_LWL_LWR;
 
   /* If the data is 2-byte aligned, then:
 
@@ -8888,7 +8888,9 @@  mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
      (c4) A block move of 8 bytes can use two LW/SW sequences or a single
 	  LD/SD sequence, and in these cases we've traditionally preferred
 	  the memory copy over the more bulky constant moves.  */
-  return size < 8;
+  return (size < 8
+	  || (align < 4 * BITS_PER_UNIT
+	      && !ISA_HAS_LWL_LWR));
 }
 
 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.