diff mbox series

[V3,5/5] RISC-V: Implement ZKSH and ZKSED extensions

Message ID 20230220070125.2291-6-shihua@iscas.ac.cn
State Accepted
Headers
Series RISC-V: Implement Scalar Cryptography Extension |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Liao Shihua Feb. 20, 2023, 7:01 a.m. UTC 
  This patch supports Zksh and Zksed extension. 
It includes instruction's machine description and built-in funtions. 

gcc/ChangeLog:

        * config/riscv/crypto.md (riscv_sm3p0_<mode>): Add ZKSED's and ZKSH's instructions.
        (riscv_sm3p1_<mode>):
        (riscv_sm4ed_<mode>):
        (riscv_sm4ks_<mode>):
        * config/riscv/riscv-builtins.cc (AVAIL): Add ZKSED's and ZKSH's AVAIL.
        * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): Add ZKSED's and ZKSH's built-in functions.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/zksed32.c: New test.
        * gcc.target/riscv/zksed64.c: New test.
        * gcc.target/riscv/zksh32.c: New test.
        * gcc.target/riscv/zksh64.c: New test.

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/crypto.md               | 48 ++++++++++++++++++++++++
 gcc/config/riscv/riscv-builtins.cc       |  4 ++
 gcc/config/riscv/riscv-scalar-crypto.def | 12 ++++++
 gcc/testsuite/gcc.target/riscv/zksed32.c | 19 ++++++++++
 gcc/testsuite/gcc.target/riscv/zksed64.c | 19 ++++++++++
 gcc/testsuite/gcc.target/riscv/zksh32.c  | 19 ++++++++++
 gcc/testsuite/gcc.target/riscv/zksh64.c  | 19 ++++++++++
 7 files changed, 140 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh64.c
diff mbox series

Patch

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 17e7440c0b5..777aa529005 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -64,6 +64,14 @@ 
     UNSPEC_SHA_512_SUM0R
     UNSPEC_SHA_512_SUM1
     UNSPEC_SHA_512_SUM1R
+
+    ;; Zksh unspecs
+    UNSPEC_SM3_P0
+    UNSPEC_SM3_P1
+
+    ;; Zksed unspecs
+    UNSPEC_SM4_ED
+    UNSPEC_SM4_KS
 ])
 
 ;; ZBKB extension
@@ -385,3 +393,43 @@ 
   "TARGET_ZKNH && TARGET_64BIT"
   "sha512sum1\t%0,%1"
   [(set_attr "type" "crypto")])
+
+ ;; ZKSH
+
+(define_insn "riscv_sm3p0_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SM3_P0))]
+  "TARGET_ZKSH"
+  "sm3p0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sm3p1_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SM3_P1))]
+  "TARGET_ZKSH"
+  "sm3p1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+;; ZKSED
+
+(define_insn "riscv_sm4ed_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")
+                  (match_operand:SI 3 "register_operand" "D03")]
+                  UNSPEC_SM4_ED))]
+  "TARGET_ZKSED"
+  "sm4ed\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sm4ks_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")
+                  (match_operand:SI 3 "register_operand" "D03")]
+                  UNSPEC_SM4_KS))]
+  "TARGET_ZKSED"
+  "sm4ks\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index ab5bd52ee7f..390f8a38309 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -113,6 +113,10 @@  AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
 AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT)
 AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
 AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
+AVAIL (crypto_zksh32, TARGET_ZKSH && !TARGET_64BIT)
+AVAIL (crypto_zksh64, TARGET_ZKSH && TARGET_64BIT)
+AVAIL (crypto_zksed32, TARGET_ZKSED && !TARGET_64BIT)
+AVAIL (crypto_zksed64, TARGET_ZKSED && TARGET_64BIT)
 AVAIL (always,     (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def
index d38aad122e5..139793c6360 100644
--- a/gcc/config/riscv/riscv-scalar-crypto.def
+++ b/gcc/config/riscv/riscv-scalar-crypto.def
@@ -80,3 +80,15 @@  DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64),
+
+// ZKSH
+RISCV_BUILTIN (sm3p0_si, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zksh32),
+RISCV_BUILTIN (sm3p0_di, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zksh64),
+RISCV_BUILTIN (sm3p1_si, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zksh32),
+RISCV_BUILTIN (sm3p1_di, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zksh64),
+
+// ZKSED
+RISCV_BUILTIN (sm4ed_si, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI, crypto_zksed32),
+RISCV_BUILTIN (sm4ed_di, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI_SI, crypto_zksed64),
+RISCV_BUILTIN (sm4ks_si, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI, crypto_zksed32),
+RISCV_BUILTIN (sm4ks_di, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI_SI, crypto_zksed64),
diff --git a/gcc/testsuite/gcc.target/riscv/zksed32.c b/gcc/testsuite/gcc.target/riscv/zksed32.c
new file mode 100644
index 00000000000..38c7ef5a62b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zksed32.c
@@ -0,0 +1,19 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zksed -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int32_t foo1(int32_t rs1, int32_t rs2, int bs)
+{
+    return __builtin_riscv_sm4ks(rs1,rs2,bs);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2, int bs)
+{
+    return __builtin_riscv_sm4ed(rs1,rs2,bs);
+}
+
+
+/* { dg-final { scan-assembler-times "sm4ks" 1 } } */
+/* { dg-final { scan-assembler-times "sm4ed" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zksed64.c b/gcc/testsuite/gcc.target/riscv/zksed64.c
new file mode 100644
index 00000000000..323d4fe1070
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zksed64.c
@@ -0,0 +1,19 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zksed -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int64_t foo1(int64_t rs1, int64_t rs2, int bs)
+{
+    return __builtin_riscv_sm4ks(rs1,rs2,bs);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2, int bs)
+{
+    return __builtin_riscv_sm4ed(rs1,rs2,bs);
+}
+
+
+/* { dg-final { scan-assembler-times "sm4ks" 1 } } */
+/* { dg-final { scan-assembler-times "sm4ed" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zksh32.c b/gcc/testsuite/gcc.target/riscv/zksh32.c
new file mode 100644
index 00000000000..edbabd8cdb7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zksh32.c
@@ -0,0 +1,19 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zksh -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int32_t foo1(int32_t rs1)
+{
+    return __builtin_riscv_sm3p0(rs1);
+}
+
+int32_t foo2(int32_t rs1)
+{
+    return __builtin_riscv_sm3p1(rs1);
+}
+
+
+/* { dg-final { scan-assembler-times "sm3p0" 1 } } */
+/* { dg-final { scan-assembler-times "sm3p1" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zksh64.c b/gcc/testsuite/gcc.target/riscv/zksh64.c
new file mode 100644
index 00000000000..832a9557880
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zksh64.c
@@ -0,0 +1,19 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zksh -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int64_t foo1(int64_t rs1)
+{
+    return __builtin_riscv_sm3p0(rs1);
+}
+
+int64_t foo2(int64_t rs1)
+{
+    return __builtin_riscv_sm3p1(rs1);
+}
+
+
+/* { dg-final { scan-assembler-times "sm3p0" 1 } } */
+/* { dg-final { scan-assembler-times "sm3p1" 1 } } */