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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id dy17-20020a05640231f100b004ad7c7c307bsi2010626edb.567.2023.02.20.02.29.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Feb 2023 02:29:02 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9D3543AA9910 for ; Mon, 20 Feb 2023 10:16:35 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTP id 197893858409 for ; Mon, 20 Feb 2023 10:15:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 197893858409 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-01 (Coremail) with SMTP id qwCowABHoNfVGvNjlPdOBg--.59272S5; Mon, 20 Feb 2023 15:01:42 +0800 (CST) From: Liao Shihua To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Liao Shihua Subject: [PATCH V3 3/5] RISC-V: Implement ZKND and ZKNE extensions Date: Mon, 20 Feb 2023 15:01:23 +0800 Message-Id: <20230220070125.2291-4-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 In-Reply-To: <20230220070125.2291-1-shihua@iscas.ac.cn> References: <20230220070125.2291-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowABHoNfVGvNjlPdOBg--.59272S5 X-Coremail-Antispam: 1UD129KBjvAXoW3tr4ftFW5uw45KFy8JFWUJwb_yoW8JFy8Zo ZYgF1kJr4fWF1I9ws3ua13Ww1DXa4vyr45Xa90qFW5tan5Jrn5Kr15Ka1rCas7trs7XF1U Zan7uFs7ZFWku3s3n29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYm7AC8VAFwI0_Xr0_Wr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r1rM28IrcIa0x kI8VCY1x0267AKxVWUCVW8JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJw A2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCF04k20xvY0x0EwIxGrwCFx2 IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v2 6r106r1rMI8E67AF67kF1VAFwI0_Jrv_JF1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67 AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IY s7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr 0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUHmhwUUUUU= X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiAwkIEWPy4r6aogAAsm X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758345499557468110?= X-GMAIL-MSGID: =?utf-8?q?1758345499557468110?= This patch supports Zkne and Zknd extension. It includes instruction's machine description and built-in funtions. gcc/ChangeLog: * config/riscv/constraints.md (D03): Add constants of bs and rnum. (DsA): * config/riscv/crypto.md (riscv_aes32dsi): Add ZKND's and ZKNE's instructions. (riscv_aes32dsmi): (riscv_aes64ds): (riscv_aes64dsm): (riscv_aes64im): (riscv_aes64ks1i): (riscv_aes64ks2): (riscv_aes32esi): (riscv_aes32esmi): (riscv_aes64es): (riscv_aes64esm): * config/riscv/riscv-builtins.cc (AVAIL): Add ZKND's and ZKNE's AVAIL. * config/riscv/riscv-scalar-crypto.def (DIRECT_BUILTIN): Add ZKND's and ZKNE's built-in functions. gcc/testsuite/ChangeLog: * gcc.target/riscv/zknd32.c: New test. * gcc.target/riscv/zknd64.c: New test. * gcc.target/riscv/zkne32.c: New test. * gcc.target/riscv/zkne64.c: New test. Co-Authored-By: SiYu Wu --- gcc/config/riscv/constraints.md | 8 ++ gcc/config/riscv/crypto.md | 121 +++++++++++++++++++++++ gcc/config/riscv/riscv-builtins.cc | 5 + gcc/config/riscv/riscv-scalar-crypto.def | 15 +++ gcc/testsuite/gcc.target/riscv/zknd32.c | 18 ++++ gcc/testsuite/gcc.target/riscv/zknd64.c | 36 +++++++ gcc/testsuite/gcc.target/riscv/zkne32.c | 18 ++++ gcc/testsuite/gcc.target/riscv/zkne64.c | 30 ++++++ 8 files changed, 251 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 3637380ee47..3f46f14b10f 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -83,6 +83,14 @@ (and (match_code "const_int") (match_test "SINGLE_BIT_MASK_OPERAND (~ival)"))) +(define_constraint "D03" + "0, 1, 2 or 3 immediate" + (match_test "IN_RANGE (ival, 0, 3)")) + +(define_constraint "DsA" + "0 - 10 immediate" + (match_test "IN_RANGE (ival, 0, 10)")) + ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is ;; not available in RV32. (define_constraint "G" diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md index a270036e39b..7568466ec97 100644 --- a/gcc/config/riscv/crypto.md +++ b/gcc/config/riscv/crypto.md @@ -33,6 +33,21 @@ ;; Zbkx unspecs UNSPEC_XPERM8 UNSPEC_XPERM4 + + ;; Zknd unspecs + UNSPEC_AES_DSI + UNSPEC_AES_DSMI + UNSPEC_AES_DS + UNSPEC_AES_DSM + UNSPEC_AES_IM + UNSPEC_AES_KS1I + UNSPEC_AES_KS2 + + ;; Zkne unspecs + UNSPEC_AES_ES + UNSPEC_AES_ESM + UNSPEC_AES_ESI + UNSPEC_AES_ESMI ]) ;; ZBKB extension @@ -126,3 +141,109 @@ "TARGET_ZBKX" "xperm8\t%0,%1,%2" [(set_attr "type" "crypto")]) + +;; ZKND extension + +(define_insn "riscv_aes32dsi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "D03")] + UNSPEC_AES_DSI))] + "TARGET_ZKND && !TARGET_64BIT" + "aes32dsi\t%0,%1,%2,%3" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes32dsmi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "D03")] + UNSPEC_AES_DSMI))] + "TARGET_ZKND && !TARGET_64BIT" + "aes32dsmi\t%0,%1,%2,%3" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64ds" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_DS))] + "TARGET_ZKND && TARGET_64BIT" + "aes64ds\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64dsm" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_DSM))] + "TARGET_ZKND && TARGET_64BIT" + "aes64dsm\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64im" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_AES_IM))] + "TARGET_ZKND && TARGET_64BIT" + "aes64im\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64ks1i" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "DsA")] + UNSPEC_AES_KS1I))] + "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT" + "aes64ks1i\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64ks2" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_KS2))] + "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT" + "aes64ks2\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +;; ZKNE extension + +(define_insn "riscv_aes32esi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "D03")] + UNSPEC_AES_ESI))] + "TARGET_ZKNE && !TARGET_64BIT" + "aes32esi\t%0,%1,%2,%3" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes32esmi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "D03")] + UNSPEC_AES_ESMI))] + "TARGET_ZKNE && !TARGET_64BIT" + "aes32esmi\t%0,%1,%2,%3" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64es" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_ES))] + "TARGET_ZKNE && TARGET_64BIT" + "aes64es\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_aes64esm" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_ESM))] + "TARGET_ZKNE && TARGET_64BIT" + "aes64esm\t%0,%1,%2" + [(set_attr "type" "crypto")]) diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index f0d60709c7d..6632009734b 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -106,6 +106,11 @@ AVAIL (crypto_zbkc32, TARGET_ZBKC && !TARGET_64BIT) AVAIL (crypto_zbkc64, TARGET_ZBKC && TARGET_64BIT) AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT) AVAIL (crypto_zbkx64, TARGET_ZBKX && TARGET_64BIT) +AVAIL (crypto_zknd32, TARGET_ZKND && !TARGET_64BIT) +AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT) +AVAIL (crypto_zkne32, TARGET_ZKNE && !TARGET_64BIT) +AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT) +AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT) AVAIL (always, (!0)) /* Construct a riscv_builtin_description from the given arguments. diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def index e4c97acbc05..fe1a4e13d2d 100644 --- a/gcc/config/riscv/riscv-scalar-crypto.def +++ b/gcc/config/riscv/riscv-scalar-crypto.def @@ -43,3 +43,18 @@ RISCV_BUILTIN (xperm4_si, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, RISCV_BUILTIN (xperm4_di, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64), RISCV_BUILTIN (xperm8_si, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32), RISCV_BUILTIN (xperm8_di, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64), + +// ZKND +DIRECT_BUILTIN (aes32dsi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zknd32), +DIRECT_BUILTIN (aes32dsmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zknd32), +DIRECT_BUILTIN (aes64ds, RISCV_DI_FTYPE_DI_DI, crypto_zknd64), +DIRECT_BUILTIN (aes64dsm, RISCV_DI_FTYPE_DI_DI, crypto_zknd64), +DIRECT_BUILTIN (aes64im, RISCV_DI_FTYPE_DI, crypto_zknd64), +DIRECT_BUILTIN (aes64ks1i, RISCV_DI_FTYPE_DI_SI, crypto_zkne_or_zknd), +DIRECT_BUILTIN (aes64ks2, RISCV_DI_FTYPE_DI_DI, crypto_zkne_or_zknd), + +// ZKNE +DIRECT_BUILTIN (aes32esi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32), +DIRECT_BUILTIN (aes32esmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32), +DIRECT_BUILTIN (aes64es, RISCV_DI_FTYPE_DI_DI, crypto_zkne64), +DIRECT_BUILTIN (aes64esm, RISCV_DI_FTYPE_DI_DI, crypto_zkne64), diff --git a/gcc/testsuite/gcc.target/riscv/zknd32.c b/gcc/testsuite/gcc.target/riscv/zknd32.c new file mode 100644 index 00000000000..203e3337d2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zknd32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zknd -mabi=ilp32d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int32_t foo1(int32_t rs1, int32_t rs2, int bs) +{ + return __builtin_riscv_aes32dsi(rs1,rs2,bs); +} + +int32_t foo2(int32_t rs1, int32_t rs2, int bs) +{ + return __builtin_riscv_aes32dsmi(rs1,rs2,bs); +} + +/* { dg-final { scan-assembler-times "aes32dsi" 1 } } */ +/* { dg-final { scan-assembler-times "aes32dsmi" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zknd64.c b/gcc/testsuite/gcc.target/riscv/zknd64.c new file mode 100644 index 00000000000..396c512fd3b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zknd64.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zknd -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int64_t foo1(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_aes64ds(rs1,rs2); +} + +int64_t foo2(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_aes64dsm(rs1,rs2); +} + +int64_t foo3(int64_t rs1, int rnum) +{ + return __builtin_riscv_aes64ks1i(rs1,rnum); +} + +int64_t foo4(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_aes64ks2(rs1,rs2); +} + +int64_t foo5(int64_t rs1) +{ + return __builtin_riscv_aes64im(rs1); +} + +/* { dg-final { scan-assembler-times "aes64ds\t" 1 } } */ +/* { dg-final { scan-assembler-times "aes64dsm" 1 } } */ +/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */ +/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */ +/* { dg-final { scan-assembler-times "aes64im" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zkne32.c b/gcc/testsuite/gcc.target/riscv/zkne32.c new file mode 100644 index 00000000000..b3bf984a140 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zkne32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zkne -mabi=ilp32d" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int32_t foo1(int32_t rs1, int32_t rs2, int bs) +{ + return __builtin_riscv_aes32esi(rs1, rs2, bs); +} + +int32_t foo2(int32_t rs1, int32_t rs2, int bs) +{ + return __builtin_riscv_aes32esmi(rs1, rs2, bs); +} + +/* { dg-final { scan-assembler-times "aes32esi" 1 } } */ +/* { dg-final { scan-assembler-times "aes32esmi" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zkne64.c b/gcc/testsuite/gcc.target/riscv/zkne64.c new file mode 100644 index 00000000000..894bab44fb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zkne64.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zkne -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include + +int64_t foo1(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_aes64es(rs1,rs2); +} + +int64_t foo2(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_aes64esm(rs1,rs2); +} + +int64_t foo3(int64_t rs1, int rnum) +{ + return __builtin_riscv_aes64ks1i(rs1,rnum); +} + +int64_t foo4(int64_t rs1, int64_t rs2) +{ + return __builtin_riscv_aes64ks2(rs1,rs2); +} + +/* { dg-final { scan-assembler-times "aes64es\t" 1 } } */ +/* { dg-final { scan-assembler-times "aes64esm" 1 } } */ +/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */ +/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */