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[8.43.85.97]) by mx.google.com with ESMTPS id d19-20020aa7d5d3000000b004aaa1cc2b47si4780826eds.155.2023.02.17.00.25.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Feb 2023 00:25:41 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@oss-cipunited-com.20200927.dkim.feishu.cn header.s=s1 header.b=ZVP9brHx; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 059BC385B523 for ; Fri, 17 Feb 2023 08:25:40 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from t03.bc.larksuite.com (t03.bc.larksuite.com [209.127.231.36]) by sourceware.org (Postfix) with UTF8SMTPS id D4B2A3858C78 for ; Fri, 17 Feb 2023 08:25:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D4B2A3858C78 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=s1; d=oss-cipunited-com.20200927.dkim.feishu.cn; t=1676622306; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=LBnfhJIr6OLfVaKiNKTOxW4gacF+zTvztG3JiGF6axw=; b=ZVP9brHx2cNWl4LPC+QJjryd1Tqzq/goa//as+rtvBuUk07SkGU8T8AuKqie6zSKhsGHuF bBKpJw6TT0zc/KJRA+aW/v9kucMFB9eqfX31Vf3tMUcZgrb5ADZLo3eMr/Wr51JGJr6zIC 252Ou3K7zYCsvzRvPZ8DbgHd2Q7H8GWXyQmagz6tYQoqGzqZU4ebHsOahpoeVe0glRcylA pF8QXOXyuG3QoOpr7gXVzuLuIq/0BJ4y8AlH7RDFLZbxosoAFs/ehoVGPxDgwZwT1xdbo5 jFfPHnBIGbSrCD76C1a9A8Mko/DtcN3l1z5pcFwDez2DMdCA9Uyy4MJykZOTmg== X-Original-From: "Junxian Zhu" X-Mailer: git-send-email 2.39.1 Subject: [PATCH] Hazard barrier return support Date: Fri, 17 Feb 2023 16:24:55 +0800 Message-Id: <20230217082258.3399094-1-zhujunxian@oss.cipunited.com> From: "Junxian Zhu" X-Lms-Return-Path: To: Cc: , , "Junxian Zhu" Mime-Version: 1.0 X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, HTML_MESSAGE, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758065948654153840?= X-GMAIL-MSGID: =?utf-8?q?1758065948654153840?= From: Junxian Zhu This patch allows a function to request clearing of all instruction and execution hazards upon normal return via __attribute__ ((use_hazard_barrier_return)). 2017-04-25 Prachi Godbole gcc/ChangeLog: * config/mips/mips.h (machine_function): New variable use_hazard_barrier_return_p. * config/mips/mips.md (UNSPEC_JRHB): New unspec. (mips_hb_return_internal): New insn pattern. * config/mips/mips.c (mips_attribute_table): Add attribute use_hazard_barrier_return. (mips_use_hazard_barrier_return_p): New static function. (mips_function_attr_inlinable_p): Likewise. (mips_compute_frame_info): Set use_hazard_barrier_return_p. Emit error for unsupported architecture choice. (mips_function_ok_for_sibcall, mips_can_use_return_insn): Return false for use_hazard_barrier_return. (mips_expand_epilogue): Emit hazard barrier return. * doc/extend.texi: Document use_hazard_barrier_return. gcc/testsuite/ChangeLog: * gcc.target/mips/hazard-barrier-return-attribute.c: New test. Signed-off-by: Junxian Zhu --- (Dragan.Mladjenovic@mediatek.com): Rehash of original patch posted by Prachi with minimal changes. Tested against mips-mti-elf with mips32r2/-EB and mips32r2/-EB/-micromips. (zhujunxian@oss.cipunited.com): Rebase and set minimal requirement to R2 --- gcc/config/mips/mips.cc | 1 + gcc/config/mips/mips.h | 3 +++ gcc/config/mips/mips.md | 15 ++++++++++++++ gcc/doc/extend.texi | 6 ++++++ .../mips/hazard-barrier-return-attribute.c | 20 +++++++++++++++++++ 5 files changed, 45 insertions(+) create mode 100644 gcc/testsuite/gcc.target/mips/hazard-barrier-return-attribute.c diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 0b25db47a22..b066a2cda75 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -630,6 +630,7 @@ static const struct attribute_spec mips_attribute_table[] = { mips_handle_use_shadow_register_set_attr, NULL }, { "keep_interrupts_masked", 0, 0, false, true, true, false, NULL, NULL }, { "use_debug_exception_return", 0, 0, false, true, true, false, NULL, NULL }, + { "use_hazard_barrier_return", 0, 0, true, false, false, false, NULL, NULL }, { NULL, 0, 0, false, false, false, false, NULL, NULL } }; diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index fbb4372864f..f664d3044e1 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -3386,6 +3386,9 @@ struct GTY(()) machine_function { /* True if GCC stored callee saved registers in the frame header. */ bool use_frame_header_for_callee_saved_regs; + + /* True if the function should generate hazard barrier return. */ + bool use_hazard_barrier_return_p; }; #endif diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 10607a57efc..ac1d77afc7d 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -159,6 +159,7 @@ ;; The `.insn' pseudo-op. UNSPEC_INSN_PSEUDO + UNSPEC_JRHB ]) (define_constants @@ -6679,6 +6680,20 @@ [(set_attr "type" "jump") (set_attr "mode" "none")]) +;; Insn to clear execution and instruction hazards while returning. +;; However, it doesn't clear hazards created by the insn in its delay slot. +;; Thus, explicitly place a nop in its delay slot. + +(define_insn "mips_hb_return_internal" + [(return) + (unspec_volatile [(match_operand 0 "pmode_register_operand" "")] + UNSPEC_JRHB)] + "" + { + return "%(jr.hb\t$31%/%)"; + } + [(set_attr "insn_count" "2")]) + ;; Normal return. (define_insn "_internal" diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 1ae68b0f20a..11920d5f07e 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -5653,6 +5653,12 @@ On MIPS targets, you can use the @code{nocompression} function attribute to locally turn off MIPS16 and microMIPS code generation. This attribute overrides the @option{-mips16} and @option{-mmicromips} options on the command line (@pxref{MIPS Options}). + +@item use_hazard_barrier_return +@cindex @code{use_hazard_barrier_return} function attribute, MIPS +This function attribute instructs the compiler to generate a hazard barrier +return that clears all execution and instruction hazards while returning, +instead of generating a normal return instruction. @end table @node MSP430 Function Attributes diff --git a/gcc/testsuite/gcc.target/mips/hazard-barrier-return-attribute.c b/gcc/testsuite/gcc.target/mips/hazard-barrier-return-attribute.c new file mode 100644 index 00000000000..3575af44dcd --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/hazard-barrier-return-attribute.c @@ -0,0 +1,20 @@ +/* Test attribute for clearing hazards while returning. */ +/* { dg-do compile } */ +/* { dg-options "isa_rev>=2 -mno-mips16" } */ + +extern int bar (); + +static int __attribute__ ((use_hazard_barrier_return)) +foo0 () +{ + return bar (); +} + +int +foo1 () +{ + return foo0 (); +} + +/* { dg-final { scan-assembler "foo0:" } } */ +/* { dg-final { scan-assembler-times "\tjr.hb\t\\\$31\n\tnop\\n" 1 } } */