diff mbox series

[V2,5/5] Implement ZKSH and ZKSED extensions

Message ID 20230216074544.2567-6-shihua@iscas.ac.cn
State Accepted
Headers
Series RISC-V: Implement Scalar Cryptography Extension |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

Liao Shihua Feb. 16, 2023, 7:45 a.m. UTC 
  This patch support Zksh and Zksed extension. 
It includes instruction's machine description, built-in funtion, and intrinsics. 

gcc/ChangeLog:

        * config/riscv/crypto.md (riscv_sm3p0_<mode>): Add ZKSH's and ZKSED's instructions.
        (riscv_sm3p1_<mode>): Likewise.
        (riscv_sm4ed_<mode>): Likewise.
        (riscv_sm4ks_<mode>): Likewise.
        * config/riscv/riscv-builtins.cc (AVAIL): Add ZKSH's and ZKSED's AVAIL.
        * config/riscv/riscv-crypto.def (RISCV_BUILTIN): Add ZKSH's and ZKSED's built-in functions.
        * config/riscv/riscv_scalar_crypto.h (__riscv_sm4ks): Add ZKSH's and ZKSED's intrinsics.
        (__riscv_sm4ed): Likewise.
        (__riscv_sm3p0): Likewise.
        (__riscv_sm3p1): Likewise.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/zksed.c: New test.
        * gcc.target/riscv/zksh.c: New test.


Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/crypto.md             | 50 +++++++++++++++++++++++++-
 gcc/config/riscv/riscv-builtins.cc     |  4 +++
 gcc/config/riscv/riscv-crypto.def      | 12 +++++++
 gcc/config/riscv/riscv_scalar_crypto.h | 20 +++++++++++
 gcc/testsuite/gcc.target/riscv/zksed.c | 20 +++++++++++
 gcc/testsuite/gcc.target/riscv/zksh.c  | 19 ++++++++++
 6 files changed, 124 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh.c
diff mbox series

Patch

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 063a8025f20..e28bdd91078 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -64,6 +64,14 @@ 
     UNSPEC_SHA_512_SUM0R
     UNSPEC_SHA_512_SUM1
     UNSPEC_SHA_512_SUM1R
+
+    ;; ZKSH unspecs
+    UNSPEC_SM3_P0
+    UNSPEC_SM3_P1
+
+    ;; ZKSED unspecs
+    UNSPEC_SM4_ED
+    UNSPEC_SM4_KS
 ])
 
 ;; ZBKB extension
@@ -384,4 +392,44 @@ 
                    UNSPEC_SHA_512_SUM1))]
   "TARGET_ZKNH && TARGET_64BIT"
   "sha512sum1\t%0,%1"
-  [(set_attr "type" "crypto")])
\ No newline at end of file
+  [(set_attr "type" "crypto")])
+
+ ;; ZKSH
+
+(define_insn "riscv_sm3p0_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SM3_P0))]
+  "TARGET_ZKSH"
+  "sm3p0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sm3p1_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SM3_P1))]
+  "TARGET_ZKSH"
+  "sm3p1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+;; ZKSED
+
+(define_insn "riscv_sm4ed_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")
+                  (match_operand:SI 3 "register_operand" "D03")]
+                  UNSPEC_SM4_ED))]
+  "TARGET_ZKSED"
+  "sm4ed\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sm4ks_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")
+                  (match_operand:SI 3 "register_operand" "D03")]
+                  UNSPEC_SM4_KS))]
+  "TARGET_ZKSED"
+  "sm4ks\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index 2a35167e6fb..18c0cce6b8b 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -113,6 +113,10 @@  AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
 AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT)
 AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
 AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
+AVAIL (crypto_zksh32, TARGET_ZKSH && !TARGET_64BIT)
+AVAIL (crypto_zksh64, TARGET_ZKSH && TARGET_64BIT)
+AVAIL (crypto_zksed32, TARGET_ZKSED && !TARGET_64BIT)
+AVAIL (crypto_zksed64, TARGET_ZKSED && TARGET_64BIT)
 AVAIL (always,     (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
diff --git a/gcc/config/riscv/riscv-crypto.def b/gcc/config/riscv/riscv-crypto.def
index 831ab8c0d01..7774b801aec 100644
--- a/gcc/config/riscv/riscv-crypto.def
+++ b/gcc/config/riscv/riscv-crypto.def
@@ -80,3 +80,15 @@  DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64),
+
+// ZKSH
+RISCV_BUILTIN (sm3p0_si, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zksh32),
+RISCV_BUILTIN (sm3p0_di, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zksh64),
+RISCV_BUILTIN (sm3p1_si, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zksh32),
+RISCV_BUILTIN (sm3p1_di, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zksh64),
+
+// ZKSED
+RISCV_BUILTIN (sm4ed_si, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI, crypto_zksed32),
+RISCV_BUILTIN (sm4ed_di, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI_SI, crypto_zksed64),
+RISCV_BUILTIN (sm4ks_si, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI, crypto_zksed32),
+RISCV_BUILTIN (sm4ks_di, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI_SI, crypto_zksed64),
diff --git a/gcc/config/riscv/riscv_scalar_crypto.h b/gcc/config/riscv/riscv_scalar_crypto.h
index 06e73a0169b..ba85483aa4a 100644
--- a/gcc/config/riscv/riscv_scalar_crypto.h
+++ b/gcc/config/riscv/riscv_scalar_crypto.h
@@ -196,3 +196,23 @@  static inline int64_t __riscv_sha512sum0(int64_t rs1)
 static inline int64_t __riscv_sha512sum1(int64_t rs1)
 	{ return _RVK_INTRIN_IMPL(sha512sum1)(rs1); }			//	SHA512SUM1
 #endif
+
+//	=== (mapping)	Zksed:	ShangMi Suite: SM4 Block Cipher Instructions
+
+static inline long __riscv_sm4ks(long rs1, long rs2, int bs)
+	{ return _RVK_INTRIN_IMPL(sm4ks)(rs1, rs2, bs); }		//	SM4KS
+
+static inline long __riscv_sm4ed(long rs1, long rs2, int bs)
+	{ return _RVK_INTRIN_IMPL(sm4ed)(rs1, rs2, bs); }		//	SM4ED
+
+//	=== (mapping)	Zksh:	ShangMi Suite: SM3 Hash Function Instructions
+
+static inline long __riscv_sm3p0(long rs1)
+	{ return _RVK_INTRIN_IMPL(sm3p0)(rs1); }				//	SM3P0
+
+static inline long __riscv_sm3p1(long rs1)
+	{ return _RVK_INTRIN_IMPL(sm3p1)(rs1); }				//	SM3P1
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/gcc/testsuite/gcc.target/riscv/zksed.c b/gcc/testsuite/gcc.target/riscv/zksed.c
new file mode 100644
index 00000000000..2c7a6ab4089
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zksed.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zksed -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include"riscv_scalar_crypto.h"
+
+long foo1(long rs1, long rs2, int bs)
+{
+    return __riscv_sm4ks(rs1,rs2,bs);
+}
+
+long foo2(long rs1, long rs2, int bs)
+{
+    return __riscv_sm4ed(rs1,rs2,bs);
+}
+
+
+/* { dg-final { scan-assembler-times "sm4ks" 1 } } */
+/* { dg-final { scan-assembler-times "sm4ed" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/zksh.c b/gcc/testsuite/gcc.target/riscv/zksh.c
new file mode 100644
index 00000000000..79485c7f3a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zksh.c
@@ -0,0 +1,19 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zksh -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include"riscv_scalar_crypto.h"
+
+long foo1(long rs1)
+{
+    return __riscv_sm3p0(rs1);
+}
+
+long foo2(long rs1)
+{
+    return __riscv_sm3p1(rs1);
+}
+
+
+/* { dg-final { scan-assembler-times "sm3p0" 1 } } */
+/* { dg-final { scan-assembler-times "sm3p1" 1 } } */