From patchwork Thu Feb 16 07:45:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liao Shihua X-Patchwork-Id: 57897 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp165397wrn; Wed, 15 Feb 2023 23:49:42 -0800 (PST) X-Google-Smtp-Source: AK7set8o2g4w9EEzP09/E1S+iRbXbeJw+diti5vYUTUZWOYKGuu5cJh3hLjHRQAysPRru2PXaHQc X-Received: by 2002:a50:ed94:0:b0:4ac:c4ed:f1d5 with SMTP id h20-20020a50ed94000000b004acc4edf1d5mr4398865edr.1.1676533782215; Wed, 15 Feb 2023 23:49:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676533782; cv=none; d=google.com; s=arc-20160816; b=tiM4xnpBbPMsJCxzjL40kALx3kWS/7Ie8rJ898d+5Or4vYUr+xIFdomlNZzCmbjtfs ava0CKunrbwtuVTEr+0a/xoSYOYJRQ2sAL9ZpECWWHyCXR942iw9FnI+1ek6emtuOa/J 9/dO+45J/EbfodyZ7LZQx8OFwsfPdF0lw1kD14wP1URz6YlS8eRxFsDO+mo6hAiB4cT7 2MI8pc0mmt56PEUw1TZtvZGpCABTXivDKhQPVMipJCqw4Xc50mrfE4A0ZhkpRRc6IJHy vsegGPC4JH8GlP5fmEG3zj8sI+1nfYx2j63CA8Vp3ciBkKOX82zIlgmSTNyokIKYUi5t B9VA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dmarc-filter:delivered-to; bh=gBAcItRKSlxQZ6j63J5tqoDYtKQLoeyYzyky89SPfCU=; b=aI8HHyHrPwOtRpO2a9K49AkPhL1byGTth6VqvwgyNyA4+aLZvmJSyBTIMryeuS4cLW Cyy/ctKUWkB9b8y7yw24N9EMvwqAbc+7asC+2h5F48WsCl6dzxJL9Az4VUd5z6UmemCA 6Lj2+GloRxo54UsTB+eOJtWKMmm9h/5AWUskRkE3XOydZ00GOFVcuJ+thB06YF79otxe 0cVY/95gSbjglmsSQ+908qf1vJhuDV1hso6sAJExJtLcd0MuLsZ/EL4LS3ZoagMFqfKg OkQJAAah7EZRJ64giYp1t2GptqzEoLr4brCPVVeRkT1EXi9V3/8EQvs3W1zlmd470/d1 6BHg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id v8-20020aa7d808000000b004acc84affc2si1484824edq.4.2023.02.15.23.49.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Feb 2023 23:49:42 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DE7853895FE4 for ; Thu, 16 Feb 2023 07:47:34 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTP id D90763858C60 for ; Thu, 16 Feb 2023 07:46:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D90763858C60 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-01 (Coremail) with SMTP id qwCowABHYNRA3+1jimRbBQ--.9693S6; Thu, 16 Feb 2023 15:46:13 +0800 (CST) From: Liao Shihua To: gcc-patches@gcc.gnu.org Cc: jiawei@iscas.ac.cn, kito.cheng@gmail.com, mjos@iki.fi, palmer@dabbelt.com, shiyulong@iscas.ac.cn, ben.marshall@pqshield.com, christoph.muellner@vrull.eu, Liao Shihua Subject: [PATCH V2 4/5] Implement ZKNH extensions Date: Thu, 16 Feb 2023 15:45:43 +0800 Message-Id: <20230216074544.2567-5-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 In-Reply-To: <20230216074544.2567-1-shihua@iscas.ac.cn> References: <20230216074544.2567-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowABHYNRA3+1jimRbBQ--.9693S6 X-Coremail-Antispam: 1UD129KBjvAXoWfXr18Kw1kXw17CrW5Gr13XFb_yoW8WrWrCo ZYgrn5XF1fJF1S9FsIkw13K3s8XF1kArn5Xa98tayFyF4rJrn5CrnYkan8Ca4vy3y7JFy5 Zws7uF4xAayUCwn5n29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYp7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r126s0DM28Irc Ia0xkI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l 84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r 4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26F4U JVW0owAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7V C0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j 6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCF04k20xvY0x0EwI xGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480 Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7 IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k2 6cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxV AFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUQSdkUUUUU= X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiBwAEEWPt1e4gCAAAsP X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757973087362668204?= X-GMAIL-MSGID: =?utf-8?q?1757973087362668204?= This patch support Zknh extension. It includes instruction's machine description, built-in funtion, and intrinsics. gcc/ChangeLog: * config/riscv/crypto.md (riscv_sha256sig0_):Add ZKNH's instructions. (riscv_sha256sig1_): Likewise. (riscv_sha256sum0_): Likewise. (riscv_sha256sum1_): Likewise. (riscv_sha512sig0h): Likewise. (riscv_sha512sig0l): Likewise. (riscv_sha512sig1h): Likewise. (riscv_sha512sig1l): Likewise. (riscv_sha512sum0r): Likewise. (riscv_sha512sum1r): Likewise. (riscv_sha512sig0): Likewise. (riscv_sha512sig1): Likewise. (riscv_sha512sum0): Likewise. (riscv_sha512sum1): Likewise. * config/riscv/riscv-builtins.cc (AVAIL): Add ZKNH's AVAIL. * config/riscv/riscv-crypto.def (RISCV_BUILTIN): Add ZKNH's built-in functions. (DIRECT_BUILTIN): Likewise. * config/riscv/riscv_scalar_crypto.h (__riscv_sha256sig0): Add ZKNH's intrinsics. (__riscv_sha256sig1): Likewise. (__riscv_sha256sum0): Likewise. (__riscv_sha256sum1): Likewise. (__riscv_sha512sig0h): Likewise. (__riscv_sha512sig0l): Likewise. (__riscv_sha512sig1h): Likewise. (__riscv_sha512sig1l): Likewise. (__riscv_sha512sum0r): Likewise. (__riscv_sha512sum1r): Likewise. (__riscv_sha512sig0): Likewise. (__riscv_sha512sig1): Likewise. (__riscv_sha512sum0): Likewise. (__riscv_sha512sum1): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/zknh-sha256.c: New test. * gcc.target/riscv/zknh-sha512-32.c: New test. * gcc.target/riscv/zknh-sha512-64.c: New test. Co-Authored-By: SiYu Wu --- gcc/config/riscv/crypto.md | 138 ++++++++++++++++++ gcc/config/riscv/riscv-builtins.cc | 2 + gcc/config/riscv/riscv-crypto.def | 22 +++ gcc/config/riscv/riscv_scalar_crypto.h | 48 ++++++ gcc/testsuite/gcc.target/riscv/zknh-sha256.c | 29 ++++ .../gcc.target/riscv/zknh-sha512-32.c | 43 ++++++ .../gcc.target/riscv/zknh-sha512-64.c | 31 ++++ 7 files changed, 313 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md index d76a872775f..063a8025f20 100644 --- a/gcc/config/riscv/crypto.md +++ b/gcc/config/riscv/crypto.md @@ -48,6 +48,22 @@ UNSPEC_AES_ESM UNSPEC_AES_ESI UNSPEC_AES_ESMI + + ;; ZKNH unspecs + UNSPEC_SHA_256_SIG0 + UNSPEC_SHA_256_SIG1 + UNSPEC_SHA_256_SUM0 + UNSPEC_SHA_256_SUM1 + UNSPEC_SHA_512_SIG0 + UNSPEC_SHA_512_SIG0H + UNSPEC_SHA_512_SIG0L + UNSPEC_SHA_512_SIG1 + UNSPEC_SHA_512_SIG1H + UNSPEC_SHA_512_SIG1L + UNSPEC_SHA_512_SUM0 + UNSPEC_SHA_512_SUM0R + UNSPEC_SHA_512_SUM1 + UNSPEC_SHA_512_SUM1R ]) ;; ZBKB extension @@ -247,3 +263,125 @@ "TARGET_ZKNE && TARGET_64BIT" "aes64esm\t%0,%1,%2" [(set_attr "type" "crypto")]) + +;; ZKNH - SHA256 + +(define_insn "riscv_sha256sig0_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SIG0))] + "TARGET_ZKNH" + "sha256sig0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha256sig1_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SIG1))] + "TARGET_ZKNH" + "sha256sig1\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha256sum0_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SUM0))] + "TARGET_ZKNH" + "sha256sum0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha256sum1_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SUM1))] + "TARGET_ZKNH" + "sha256sum1\t%0,%1" + [(set_attr "type" "crypto")]) + +;; ZKNH - SHA512 + +(define_insn "riscv_sha512sig0h" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG0H))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig0h\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig0l" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG0L))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig0l\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig1h" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG1H))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig1h\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig1l" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG1L))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig1l\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sum0r" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SUM0R))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sum0r\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sum1r" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SUM1R))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sum1r\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig0" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_SHA_512_SIG0))] + "TARGET_ZKNH && TARGET_64BIT" + "sha512sig0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sig1" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_SHA_512_SIG1))] + "TARGET_ZKNH && TARGET_64BIT" + "sha512sig1\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sum0" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_SHA_512_SUM0))] + "TARGET_ZKNH && TARGET_64BIT" + "sha512sum0\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_sha512sum1" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_SHA_512_SUM1))] + "TARGET_ZKNH && TARGET_64BIT" + "sha512sum1\t%0,%1" + [(set_attr "type" "crypto")]) \ No newline at end of file diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index b92619f99e4..2a35167e6fb 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -111,6 +111,8 @@ AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT) AVAIL (crypto_zkne32, TARGET_ZKNE && !TARGET_64BIT) AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT) AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT) +AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT) +AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT) AVAIL (always, (!0)) /* Construct a riscv_builtin_description from the given arguments. diff --git a/gcc/config/riscv/riscv-crypto.def b/gcc/config/riscv/riscv-crypto.def index 57d031c2e09..831ab8c0d01 100644 --- a/gcc/config/riscv/riscv-crypto.def +++ b/gcc/config/riscv/riscv-crypto.def @@ -58,3 +58,25 @@ DIRECT_BUILTIN (aes32esi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32), DIRECT_BUILTIN (aes32esmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32), DIRECT_BUILTIN (aes64es, RISCV_DI_FTYPE_DI_DI, crypto_zkne64), DIRECT_BUILTIN (aes64esm, RISCV_DI_FTYPE_DI_DI, crypto_zkne64), + +// ZKNH +RISCV_BUILTIN (sha256sig0_si, "sha256sig0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32), +RISCV_BUILTIN (sha256sig0_di, "sha256sig0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64), +RISCV_BUILTIN (sha256sig1_si, "sha256sig1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32), +RISCV_BUILTIN (sha256sig1_di, "sha256sig1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64), +RISCV_BUILTIN (sha256sum0_si, "sha256sum0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32), +RISCV_BUILTIN (sha256sum0_di, "sha256sum0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64), +RISCV_BUILTIN (sha256sum1_si, "sha256sum1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32), +RISCV_BUILTIN (sha256sum1_di, "sha256sum1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64), + +DIRECT_BUILTIN (sha512sig0h, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), +DIRECT_BUILTIN (sha512sig0l, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), +DIRECT_BUILTIN (sha512sig1h, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), +DIRECT_BUILTIN (sha512sig1l, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), +DIRECT_BUILTIN (sha512sum0r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), +DIRECT_BUILTIN (sha512sum1r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32), + +DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, crypto_zknh64), +DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64), +DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64), +DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64), diff --git a/gcc/config/riscv/riscv_scalar_crypto.h b/gcc/config/riscv/riscv_scalar_crypto.h index 3418bcf5774..06e73a0169b 100644 --- a/gcc/config/riscv/riscv_scalar_crypto.h +++ b/gcc/config/riscv/riscv_scalar_crypto.h @@ -148,3 +148,51 @@ static inline int64_t __riscv_aes64es(int64_t rs1, int64_t rs2) static inline int64_t __riscv_aes64esm(int64_t rs1, int64_t rs2) { return _RVK_INTRIN_IMPL(aes64esm)(rs1, rs2); } // AES64ESM #endif + +// === (mapping) Zknh: NIST Suite: Hash Function Instructions + +static inline long __riscv_sha256sig0(long rs1) + { return _RVK_INTRIN_IMPL(sha256sig0)(rs1); } // SHA256SIG0 + +static inline long __riscv_sha256sig1(long rs1) + { return _RVK_INTRIN_IMPL(sha256sig1)(rs1); } // SHA256SIG1 + +static inline long __riscv_sha256sum0(long rs1) + { return _RVK_INTRIN_IMPL(sha256sum0)(rs1); } // SHA256SUM0 + +static inline long __riscv_sha256sum1(long rs1) + { return _RVK_INTRIN_IMPL(sha256sum1)(rs1); } // SHA256SUM1 + +#ifdef RVKINTRIN_RV32 +static inline int32_t __riscv_sha512sig0h(int32_t rs1, int32_t rs2) + { return _RVK_INTRIN_IMPL(sha512sig0h)(rs1, rs2); } // SHA512SIG0H + +static inline int32_t __riscv_sha512sig0l(int32_t rs1, int32_t rs2) + { return _RVK_INTRIN_IMPL(sha512sig0l)(rs1, rs2); } // SHA512SIG0L + +static inline int32_t __riscv_sha512sig1h(int32_t rs1, int32_t rs2) + { return _RVK_INTRIN_IMPL(sha512sig1h)(rs1, rs2); } // SHA512SIG1H + +static inline int32_t __riscv_sha512sig1l(int32_t rs1, int32_t rs2) + { return _RVK_INTRIN_IMPL(sha512sig1l)(rs1, rs2); } // SHA512SIG1L + +static inline int32_t __riscv_sha512sum0r(int32_t rs1, int32_t rs2) + { return _RVK_INTRIN_IMPL(sha512sum0r)(rs1, rs2); } // SHA512SUM0R + +static inline int32_t __riscv_sha512sum1r(int32_t rs1, int32_t rs2) + { return _RVK_INTRIN_IMPL(sha512sum1r)(rs1, rs2); } // SHA512SUM1R +#endif + +#ifdef RVKINTRIN_RV64 +static inline int64_t __riscv_sha512sig0(int64_t rs1) + { return _RVK_INTRIN_IMPL(sha512sig0)(rs1); } // SHA512SIG0 + +static inline int64_t __riscv_sha512sig1(int64_t rs1) + { return _RVK_INTRIN_IMPL(sha512sig1)(rs1); } // SHA512SIG1 + +static inline int64_t __riscv_sha512sum0(int64_t rs1) + { return _RVK_INTRIN_IMPL(sha512sum0)(rs1); } // SHA512SUM0 + +static inline int64_t __riscv_sha512sum1(int64_t rs1) + { return _RVK_INTRIN_IMPL(sha512sum1)(rs1); } // SHA512SUM1 +#endif diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha256.c b/gcc/testsuite/gcc.target/riscv/zknh-sha256.c new file mode 100644 index 00000000000..88bf01eb279 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zknh-sha256.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zknh -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include"riscv_scalar_crypto.h" +long foo1(long rs1) +{ + return __riscv_sha256sig0(rs1); +} + +long foo2(long rs1) +{ + return __riscv_sha256sig1(rs1); +} + +long foo3(long rs1) +{ + return __riscv_sha256sum0(rs1); +} + +long foo4(long rs1) +{ + return __riscv_sha256sum1(rs1); +} + +/* { dg-final { scan-assembler-times "sha256sig0" 1 } } */ +/* { dg-final { scan-assembler-times "sha256sig1" 1 } } */ +/* { dg-final { scan-assembler-times "sha256sum0" 1 } } */ +/* { dg-final { scan-assembler-times "sha256sum1" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c b/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c new file mode 100644 index 00000000000..dcea6ad1536 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zknh -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include"riscv_scalar_crypto.h" + +int32_t foo1(int32_t rs1, int32_t rs2) +{ + return __riscv_sha512sig0h(rs1,rs2); +} + +int32_t foo2(int32_t rs1, int32_t rs2) +{ + return __riscv_sha512sig0l(rs1,rs2); +} + +int32_t foo3(int32_t rs1, int32_t rs2) +{ + return __riscv_sha512sig1h(rs1,rs2); +} + +int32_t foo4(int32_t rs1, int32_t rs2) +{ + return __riscv_sha512sig1l(rs1,rs2); +} + +int32_t foo5(int32_t rs1, int32_t rs2) +{ + return __riscv_sha512sum0r(rs1,rs2); +} + +int32_t foo6(int32_t rs1, int32_t rs2) +{ + return __riscv_sha512sum1r(rs1,rs2); +} + +/* { dg-final { scan-assembler-times "sha512sig0h" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sig0l" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sig1h" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sig1l" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sum0r" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sum1r" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c b/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c new file mode 100644 index 00000000000..ed87e1e93bb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zknh -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include"riscv_scalar_crypto.h" + +int64_t foo1(int64_t rs1) +{ + return __riscv_sha512sig0(rs1); +} + +int64_t foo2(int64_t rs1) +{ + return __riscv_sha512sig1(rs1); +} + +int64_t foo3(int64_t rs1) +{ + return __riscv_sha512sum0(rs1); +} + +int64_t foo4(int64_t rs1) +{ + return __riscv_sha512sum1(rs1); +} + + +/* { dg-final { scan-assembler-times "sha512sig0" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sig1" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sum0" 1 } } */ +/* { dg-final { scan-assembler-times "sha512sum1" 1 } } */