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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id uo39-20020a170907cc2700b008b150a6dab1si1298511ejc.208.2023.02.15.23.50.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Feb 2023 23:50:04 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A76FD389942B for ; Thu, 16 Feb 2023 07:47:43 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTP id 0A5293858409 for ; Thu, 16 Feb 2023 07:46:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0A5293858409 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [39.170.88.238]) by APP-01 (Coremail) with SMTP id qwCowABHYNRA3+1jimRbBQ--.9693S4; Thu, 16 Feb 2023 15:46:11 +0800 (CST) From: Liao Shihua To: gcc-patches@gcc.gnu.org Cc: jiawei@iscas.ac.cn, kito.cheng@gmail.com, mjos@iki.fi, palmer@dabbelt.com, shiyulong@iscas.ac.cn, ben.marshall@pqshield.com, christoph.muellner@vrull.eu, Liao Shihua Subject: [PATCH V2 2/5] Implement ZBKB, ZBKC and ZBKX extensions Date: Thu, 16 Feb 2023 15:45:41 +0800 Message-Id: <20230216074544.2567-3-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.1.windows.1 In-Reply-To: <20230216074544.2567-1-shihua@iscas.ac.cn> References: <20230216074544.2567-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowABHYNRA3+1jimRbBQ--.9693S4 X-Coremail-Antispam: 1UD129KBjvAXoWfCFyrWFWUtryUCw15AFy7Jrb_yoW5JF47Zo Z3trs5AF4rGFyI9ws09w4fXrnrXF1jyr4rXa90qrWrt3Z5Jr1Fkw1a9an8Aasaqr1xXFyU Za97uan7XFWkWas3n29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYH7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r15M28IrcIa0x kI8VCY1x0267AKxVW8JVW5JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j6F4UM2 8EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Cr1j6rxd M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxAIw28IcxkI7VAKI48JMx C20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAF wI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20x vE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v2 0xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AKxV W8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUjYiiDUUUUU== X-Originating-IP: [39.170.88.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiCQoEEWPt2tcQSgAAsP X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757973110370660826?= X-GMAIL-MSGID: =?utf-8?q?1757973110370660826?= This patch support Zkbk, Zbkc and Zkbx extension. It includes instruction's machine description, built-in funtion, and intrinsics. It is worth mentioning that this patch only adds instructions in Zbkb but no longer in Zbb. If any instructions both in Zbb and Zbkb, they will be generated by code generator instead of built-in functions and intrinsics. gcc/ChangeLog: * config.gcc: Add intrinsics header in extra_headers. * config/riscv/bitmanip.md: Add TARGET_ZBKB if these instructions are included in ZBKB extension. * config/riscv/riscv-builtins.cc (AVAIL): Add ZBKB's,ZBKC's,ZBKX's AVAIL. * config/riscv/riscv.md: include crypto.md. * config/riscv/crypto.md: Scalar Cryptography Machine description file. * config/riscv/riscv-crypto.def: Scalar Cryptography built-in function file. * config/riscv/riscv_scalar_crypto.h: Scalar Cryptography intrinsics header. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbkb32.c: New test. * gcc.target/riscv/zbkb64.c: New test. * gcc.target/riscv/zbkc32.c: New test. * gcc.target/riscv/zbkc64.c: New test. * gcc.target/riscv/zbkx32.c: New test. * gcc.target/riscv/zbkx64.c: New test. Co-Authored-By: SiYu Wu --- gcc/config.gcc | 2 +- gcc/config/riscv/bitmanip.md | 20 ++-- gcc/config/riscv/crypto.md | 130 ++++++++++++++++++++++++ gcc/config/riscv/riscv-builtins.cc | 7 ++ gcc/config/riscv/riscv-crypto.def | 45 ++++++++ gcc/config/riscv/riscv.md | 4 +- gcc/config/riscv/riscv_scalar_crypto.h | 104 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zbkb32.c | 36 +++++++ gcc/testsuite/gcc.target/riscv/zbkb64.c | 28 +++++ gcc/testsuite/gcc.target/riscv/zbkc32.c | 17 ++++ gcc/testsuite/gcc.target/riscv/zbkc64.c | 17 ++++ gcc/testsuite/gcc.target/riscv/zbkx32.c | 18 ++++ gcc/testsuite/gcc.target/riscv/zbkx64.c | 18 ++++ 13 files changed, 434 insertions(+), 12 deletions(-) create mode 100644 gcc/config/riscv/crypto.md create mode 100644 gcc/config/riscv/riscv-crypto.def create mode 100644 gcc/config/riscv/riscv_scalar_crypto.h create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c diff --git a/gcc/config.gcc b/gcc/config.gcc index f0958e1c959..951b92b2028 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -532,7 +532,7 @@ riscv*) extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o riscv-vsetvl.o" extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o" d_target_objs="riscv-d.o" - extra_headers="riscv_vector.h" + extra_headers="riscv_vector.h riscv_scalar_crypto.h" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc" target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.h" ;; diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 14d18edbe62..f076ba35832 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -189,7 +189,7 @@ [(set (match_operand:X 0 "register_operand" "=r") (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r")) (match_operand:X 2 "register_operand" "r")))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" "n\t%0,%2,%1" [(set_attr "type" "bitmanip") (set_attr "mode" "")]) @@ -203,7 +203,7 @@ (const_int 0))) (match_operand:DI 2 "register_operand"))) (clobber (match_operand:DI 3 "register_operand"))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" [(set (match_dup 3) (ashiftrt:DI (match_dup 1) (const_int 63))) (set (match_dup 0) (and:DI (not:DI (match_dup 3)) (match_dup 2)))]) @@ -211,7 +211,7 @@ [(set (match_operand:X 0 "register_operand" "=r") (not:X (xor:X (match_operand:X 1 "register_operand" "r") (match_operand:X 2 "register_operand" "r"))))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" "xnor\t%0,%1,%2" [(set_attr "type" "bitmanip") (set_attr "mode" "")]) @@ -277,7 +277,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (rotatert:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "arith_operand" "rI")))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" "ror%i2%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -285,7 +285,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (rotatert:DI (match_operand:DI 1 "register_operand" "r") (match_operand:QI 2 "arith_operand" "rI")))] - "TARGET_64BIT && TARGET_ZBB" + "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)" "ror%i2\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -293,7 +293,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r"))))] - "TARGET_64BIT && TARGET_ZBB" + "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)" "rorw\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -301,7 +301,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (rotate:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r")))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" "rol%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -309,7 +309,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (rotate:DI (match_operand:DI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r")))] - "TARGET_64BIT && TARGET_ZBB" + "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)" "rol\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -317,7 +317,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r"))))] - "TARGET_64BIT && TARGET_ZBB" + "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)" "rolw\t%0,%1,%2" [(set_attr "type" "bitmanip")]) @@ -332,7 +332,7 @@ (define_insn "bswap2" [(set (match_operand:X 0 "register_operand" "=r") (bswap:X (match_operand:X 1 "register_operand" "r")))] - "TARGET_ZBB" + "TARGET_ZBB || TARGET_ZBKB" "rev8\t%0,%1" [(set_attr "type" "bitmanip")]) diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md new file mode 100644 index 00000000000..6792f19ed68 --- /dev/null +++ b/gcc/config/riscv/crypto.md @@ -0,0 +1,130 @@ +;; Machine description for RISC-V Scalar Cryptography extensions. +;; Copyright (C) 2023 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_c_enum "unspec" [ + ;; ZBKB unspecs + UNSPEC_BREV8 + UNSPEC_ZIP + UNSPEC_UNZIP + UNSPEC_PACK + UNSPEC_PACKH + UNSPEC_PACKW + + ;; ZBKC unspecs + UNSPEC_CLMUL + UNSPEC_CLMULH + + ;; ZBKX unspecs + UNSPEC_XPERM8 + UNSPEC_XPERM4 + + +]) + +;; ZBKB extension +(define_insn "riscv_brev8_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_BREV8))] + "TARGET_ZBKB" + "brev8\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_zip" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_ZIP))] + "TARGET_ZBKB && !TARGET_64BIT" + "zip\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_unzip" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_UNZIP))] + "TARGET_ZBKB && !TARGET_64BIT" + "unzip\t%0,%1" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_pack_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:HISI 1 "register_operand" "r") + (match_operand:HISI 2 "register_operand" "r")] + UNSPEC_PACK))] + "TARGET_ZBKB" + "pack\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_packh_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:QI 1 "register_operand" "r") + (match_operand:QI 2 "register_operand" "r")] + UNSPEC_PACKH))] + "TARGET_ZBKB" + "packh\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_packw" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:HI 1 "register_operand" "r") + (match_operand:HI 2 "register_operand" "r")] + UNSPEC_PACKW))] + "TARGET_ZBKB && TARGET_64BIT" + "packw\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +;; ZBKC extension + +(define_insn "riscv_clmul_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_CLMUL))] + "TARGET_ZBKC" + "clmul\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_clmulh_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_CLMULH))] + "TARGET_ZBKC" + "clmulh\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +;; ZBKX extension + +(define_insn "riscv_xperm4_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_XPERM4))] + "TARGET_ZBKX" + "xperm4\t%0,%1,%2" + [(set_attr "type" "crypto")]) + +(define_insn "riscv_xperm8_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_XPERM8))] + "TARGET_ZBKX" + "xperm8\t%0,%1,%2" + [(set_attr "type" "crypto")]) diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index ded91e17554..e9c2d92f0d3 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -100,6 +100,12 @@ AVAIL (zero32, TARGET_ZICBOZ && !TARGET_64BIT) AVAIL (zero64, TARGET_ZICBOZ && TARGET_64BIT) AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT) AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT) +AVAIL (crypto_zbkb32, TARGET_ZBKB && !TARGET_64BIT) +AVAIL (crypto_zbkb64, TARGET_ZBKB && TARGET_64BIT) +AVAIL (crypto_zbkc32, TARGET_ZBKC && !TARGET_64BIT) +AVAIL (crypto_zbkc64, TARGET_ZBKC && TARGET_64BIT) +AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT) +AVAIL (crypto_zbkx64, TARGET_ZBKX && TARGET_64BIT) AVAIL (always, (!0)) /* Construct a riscv_builtin_description from the given arguments. @@ -152,6 +158,7 @@ AVAIL (always, (!0)) RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D static const struct riscv_builtin_description riscv_builtins[] = { + #include "riscv-crypto.def" #include "riscv-cmo.def" DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float), diff --git a/gcc/config/riscv/riscv-crypto.def b/gcc/config/riscv/riscv-crypto.def new file mode 100644 index 00000000000..ebb82629296 --- /dev/null +++ b/gcc/config/riscv/riscv-crypto.def @@ -0,0 +1,45 @@ +/* Builtin functions for RISC-V Scalar Cryptography extensions. + Copyright (C) 2023 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +// ZBKB +RISCV_BUILTIN (pack_sihi, "pack", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_HI_HI, crypto_zbkb32), +RISCV_BUILTIN (pack_disi, "pack", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_SI_SI, crypto_zbkb64), + +RISCV_BUILTIN (packh_si, "packh", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_QI_QI, crypto_zbkb32), +RISCV_BUILTIN (packh_di, "packh", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_QI_QI, crypto_zbkb64), + +RISCV_BUILTIN (packw, "packw", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_HI_HI, crypto_zbkb64), + +RISCV_BUILTIN (zip, "zip_32", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32), +RISCV_BUILTIN (unzip, "unzip_32", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32), + +RISCV_BUILTIN (brev8_si, "brev8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32), +RISCV_BUILTIN (brev8_di, "brev8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zbkb64), + +// ZBKC +RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkc32), +RISCV_BUILTIN (clmul_di, "clmul", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkc64), +RISCV_BUILTIN (clmulh_si, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkc32), +RISCV_BUILTIN (clmulh_di, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkc64), + +// ZBKX +RISCV_BUILTIN (xperm4_si, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32), +RISCV_BUILTIN (xperm4_di, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64), +RISCV_BUILTIN (xperm8_si, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32), +RISCV_BUILTIN (xperm8_di, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64), diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index c8adc5af5d2..c424a82dcbd 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -242,6 +242,7 @@ ;; bitmanip bit manipulation instructions ;; rotate rotation instructions ;; atomic atomic instructions +;; crypto cryptography instructions ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. ;; rdvlenb vector byte length vlenb csrr read ;; rdvl vector length vl csrr read @@ -333,7 +334,7 @@ "unknown,branch,jump,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate, - atomic,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts, + atomic,crypto,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts, vldux,vldox,vstux,vstox,vldff,vldr,vstr, vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp, vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov, @@ -3092,3 +3093,4 @@ (include "generic.md") (include "sifive-7.md") (include "vector.md") +(include "crypto.md") diff --git a/gcc/config/riscv/riscv_scalar_crypto.h b/gcc/config/riscv/riscv_scalar_crypto.h new file mode 100644 index 00000000000..2e2644fa323 --- /dev/null +++ b/gcc/config/riscv/riscv_scalar_crypto.h @@ -0,0 +1,104 @@ +/* RISC-V Scalar Cryptography Extension intrinsics include file. + Copyright (C) 2023 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef _RISCV_SCALAR_CRYPTO_H +#define _RISCV_SCALAR_CRYPTO_H +#endif // _RISCV_SCALAR_CRYPTO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(__riscv_xlen) && !defined(RVKINTRIN_EMULATE) +#warning "Target is not RISC-V. Enabling insecure emulation." +#define RVKINTRIN_EMULATE 1 +#endif + +// intrinsics via compiler builtins +#include +#define _RVK_INTRIN_IMPL(s) __builtin_riscv_##s + + +// set type if not already set +#if !defined(RVKINTRIN_RV32) && !defined(RVKINTRIN_RV64) +#if __riscv_xlen == 32 +#define RVKINTRIN_RV32 +#elif __riscv_xlen == 64 +#define RVKINTRIN_RV64 +#else +#error "__riscv_xlen not valid." +#endif +#endif + +// Mappings to implementation + +// === (mapping) Zbkb: Bitmanipulation instructions for Cryptography + +#ifdef RVKINTRIN_RV32 +static inline int32_t __riscv_pack(int16_t rs1, int16_t rs2) + { return _RVK_INTRIN_IMPL(pack)(rs1, rs2); } // PACK + +static inline int32_t __riscv_packh(int8_t rs1, int8_t rs2) + { return _RVK_INTRIN_IMPL(packh)(rs1, rs2); } // PACKH +#endif + +#ifdef RVKINTRIN_RV64 +static inline int64_t __riscv_pack(int32_t rs1, int32_t rs2) + { return _RVK_INTRIN_IMPL(pack)(rs1, rs2); } // PACK + +static inline int64_t __riscv_packh(int8_t rs1, int8_t rs2) + { return _RVK_INTRIN_IMPL(packh)(rs1, rs2); } // PACKH + +static inline int64_t __riscv_packw(int16_t rs1, int16_t rs2) + { return _RVK_INTRIN_IMPL(packw)(rs1, rs2); } // PACKW + +#endif + +static inline long __riscv_brev8(long rs1) + { return _RVK_INTRIN_IMPL(brev8)(rs1); } // BREV8 (GREVI) + +#ifdef RVKINTRIN_RV32 +static inline int32_t __riscv_zip(int32_t rs1) + { return _RVK_INTRIN_IMPL(zip_32)(rs1); } // ZIP (SHFLI) + +static inline int32_t __riscv_unzip(int32_t rs1) + { return _RVK_INTRIN_IMPL(unzip_32)(rs1); } // UNZIP (UNSHFLI) +#endif + +// === (mapping) Zbkc: Carry-less multiply instructions + +static inline long __riscv_clmul(long rs1, long rs2) + { return _RVK_INTRIN_IMPL(clmul)(rs1, rs2); } // CLMUL + +static inline long __riscv_clmulh(long rs1, long rs2) + { return _RVK_INTRIN_IMPL(clmulh)(rs1, rs2); } // CLMULH + +// === (mapping) Zbkx: Crossbar permutation instructions + + +static inline long __riscv_xperm8(long rs1, long rs2) + { return _RVK_INTRIN_IMPL(xperm8_64)(rs1, rs2); } // XPERM8 + +static inline long __riscv_xperm4(long rs1, long rs2) + { return _RVK_INTRIN_IMPL(xperm4_64)(rs1, rs2); } // XPERM4 diff --git a/gcc/testsuite/gcc.target/riscv/zbkb32.c b/gcc/testsuite/gcc.target/riscv/zbkb32.c new file mode 100644 index 00000000000..c37492ae32b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkb32.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zbkb -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include "riscv_scalar_crypto.h" + +int32_t foo1(int16_t rs1, int16_t rs2) +{ + return __riscv_pack(rs1, rs2); +} + +int32_t foo2(int8_t rs1, int8_t rs2) +{ + return __riscv_packh(rs1, rs2); +} + +int32_t foo3(int32_t rs1) +{ + return __riscv_brev8(rs1); +} + +int32_t foo4(int32_t rs1) +{ + return __riscv_zip(rs1); +} + +int32_t foo5(int32_t rs1) +{ + return __riscv_unzip(rs1); +} + +/* { dg-final { scan-assembler-times "pack\t" 1 } } */ +/* { dg-final { scan-assembler-times "packh" 1 } } */ +/* { dg-final { scan-assembler-times "brev8" 1 } } */ +/* { dg-final { scan-assembler-times "zip" 2 } } */ +/* { dg-final { scan-assembler-times "unzip" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkb64.c b/gcc/testsuite/gcc.target/riscv/zbkb64.c new file mode 100644 index 00000000000..e7771f73394 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkb64.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zbkb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +#include "riscv_scalar_crypto.h" + +int64_t foo1(int32_t rs1, int32_t rs2) +{ + return __riscv_pack(rs1, rs2); +} + +int64_t foo2(int8_t rs1, int8_t rs2) +{ + return __riscv_packh(rs1, rs2); +} + +int64_t foo3(int16_t rs1, int16_t rs2) +{ + return __riscv_packw(rs1, rs2); +} + +int64_t foo4(int64_t rs1, int64_t rs2) +{ + return __riscv_brev8(rs1); +} +/* { dg-final { scan-assembler-times "pack\t" 1 } } */ +/* { dg-final { scan-assembler-times "packh" 1 } } */ +/* { dg-final { scan-assembler-times "packw" 1 } } */ +/* { dg-final { scan-assembler-times "brev8" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkc32.c b/gcc/testsuite/gcc.target/riscv/zbkc32.c new file mode 100644 index 00000000000..13b09f2879b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkc32.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zbkc -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +#include "riscv_scalar_crypto.h" + +int32_t foo1(int32_t rs1, int32_t rs2) +{ + return __riscv_clmul(rs1, rs2); +} + +int32_t foo2(int32_t rs1, int32_t rs2) +{ + return __riscv_clmulh(rs1, rs2); +} + +/* { dg-final { scan-assembler-times "clmul\t" 1 } } */ +/* { dg-final { scan-assembler-times "clmulh" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkc64.c b/gcc/testsuite/gcc.target/riscv/zbkc64.c new file mode 100644 index 00000000000..6493a83c57a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkc64.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zbkc -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ +#include "riscv_scalar_crypto.h" + +int64_t foo1(int64_t rs1, int64_t rs2) +{ + return __riscv_clmul(rs1, rs2); +} + +int64_t foo2(int64_t rs1, int64_t rs2) +{ + return __riscv_clmulh(rs1, rs2); +} + +/* { dg-final { scan-assembler-times "clmul\t" 1 } } */ +/* { dg-final { scan-assembler-times "clmulh" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkx32.c b/gcc/testsuite/gcc.target/riscv/zbkx32.c new file mode 100644 index 00000000000..426cce88425 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkx32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_zbkx -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include "riscv_scalar_crypto.h" + +int32_t foo3(int32_t rs1, int32_t rs2) +{ + return __riscv_xperm8(rs1, rs2); +} + +int32_t foo4(int32_t rs1, int32_t rs2) +{ + return __riscv_xperm4(rs1, rs2); +} + +/* { dg-final { scan-assembler-times "xperm8" 1 } } */ +/* { dg-final { scan-assembler-times "xperm4" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zbkx64.c b/gcc/testsuite/gcc.target/riscv/zbkx64.c new file mode 100644 index 00000000000..7bc09bd77be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbkx64.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zbkx -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ + +#include "riscv_scalar_crypto.h" + +int64_t foo1(int64_t rs1, int64_t rs2) +{ + return __riscv_xperm8(rs1, rs2); +} + +int64_t foo2(int64_t rs1, int64_t rs2) +{ + return __riscv_xperm4(rs1, rs2); +} + +/* { dg-final { scan-assembler-times "xperm8" 1 } } */ +/* { dg-final { scan-assembler-times "xperm4" 1 } } */