diff mbox series

RISC-V: Add the res of all mask C api tests

Message ID 20230216034001.17197-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Add the res of all mask C api tests |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Feb. 16, 2023, 3:40 a.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vcpop_m_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vcpop_m_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vcpop_m_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vfirst_m_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vfirst_m_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vfirst_m_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vlm_v-1.c: New test.
        * gcc.target/riscv/rvv/base/vlm_v-2.c: New test.
        * gcc.target/riscv/rvv/base/vlm_v-3.c: New test.
        * gcc.target/riscv/rvv/base/vsm_v-1.c: New test.
        * gcc.target/riscv/rvv/base/vsm_v-2.c: New test.
        * gcc.target/riscv/rvv/base/vsm_v-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vcpop_m_m-1.c   | 104 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vcpop_m_m-2.c   | 104 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vcpop_m_m-3.c   | 104 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vfirst_m_m-1.c  | 104 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vfirst_m_m-2.c  | 104 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vfirst_m_m-3.c  | 104 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vlm_v-1.c       |  55 +++++++++
 .../gcc.target/riscv/rvv/base/vlm_v-2.c       |  55 +++++++++
 .../gcc.target/riscv/rvv/base/vlm_v-3.c       |  55 +++++++++
 .../gcc.target/riscv/rvv/base/vsm_v-1.c       |  55 +++++++++
 .../gcc.target/riscv/rvv/base/vsm_v-2.c       |  55 +++++++++
 .../gcc.target/riscv/rvv/base/vsm_v-3.c       |  55 +++++++++
 12 files changed, 954 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-3.c
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-1.c
new file mode 100644
index 00000000000..5ac335ac1ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-1.c
@@ -0,0 +1,104 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+uint64_t test___riscv_vcpop_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b1(op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b2(op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b4(op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b8(op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b16(op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b32(op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b64(op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b1_m(mask,op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b2_m(mask,op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b4_m(mask,op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b8_m(mask,op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b16_m(mask,op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b32_m(mask,op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b64_m(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-2.c
new file mode 100644
index 00000000000..76c3ce31e39
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-2.c
@@ -0,0 +1,104 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+uint64_t test___riscv_vcpop_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b1(op1,31);
+}
+
+
+uint64_t test___riscv_vcpop_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b2(op1,31);
+}
+
+
+uint64_t test___riscv_vcpop_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b4(op1,31);
+}
+
+
+uint64_t test___riscv_vcpop_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b8(op1,31);
+}
+
+
+uint64_t test___riscv_vcpop_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b16(op1,31);
+}
+
+
+uint64_t test___riscv_vcpop_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b32(op1,31);
+}
+
+
+uint64_t test___riscv_vcpop_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b64(op1,31);
+}
+
+
+uint64_t test___riscv_vcpop_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b1_m(mask,op1,31);
+}
+
+
+uint64_t test___riscv_vcpop_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b2_m(mask,op1,31);
+}
+
+
+uint64_t test___riscv_vcpop_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b4_m(mask,op1,31);
+}
+
+
+uint64_t test___riscv_vcpop_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b8_m(mask,op1,31);
+}
+
+
+uint64_t test___riscv_vcpop_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b16_m(mask,op1,31);
+}
+
+
+uint64_t test___riscv_vcpop_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b32_m(mask,op1,31);
+}
+
+
+uint64_t test___riscv_vcpop_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b64_m(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-3.c
new file mode 100644
index 00000000000..eeab2c000e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vcpop_m_m-3.c
@@ -0,0 +1,104 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+uint64_t test___riscv_vcpop_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b1(op1,32);
+}
+
+
+uint64_t test___riscv_vcpop_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b2(op1,32);
+}
+
+
+uint64_t test___riscv_vcpop_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b4(op1,32);
+}
+
+
+uint64_t test___riscv_vcpop_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b8(op1,32);
+}
+
+
+uint64_t test___riscv_vcpop_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b16(op1,32);
+}
+
+
+uint64_t test___riscv_vcpop_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b32(op1,32);
+}
+
+
+uint64_t test___riscv_vcpop_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b64(op1,32);
+}
+
+
+uint64_t test___riscv_vcpop_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b1_m(mask,op1,32);
+}
+
+
+uint64_t test___riscv_vcpop_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b2_m(mask,op1,32);
+}
+
+
+uint64_t test___riscv_vcpop_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b4_m(mask,op1,32);
+}
+
+
+uint64_t test___riscv_vcpop_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b8_m(mask,op1,32);
+}
+
+
+uint64_t test___riscv_vcpop_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b16_m(mask,op1,32);
+}
+
+
+uint64_t test___riscv_vcpop_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b32_m(mask,op1,32);
+}
+
+
+uint64_t test___riscv_vcpop_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vcpop_m_b64_m(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-1.c
new file mode 100644
index 00000000000..13631233a12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-1.c
@@ -0,0 +1,104 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+long test___riscv_vfirst_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b1(op1,vl);
+}
+
+
+long test___riscv_vfirst_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b2(op1,vl);
+}
+
+
+long test___riscv_vfirst_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b4(op1,vl);
+}
+
+
+long test___riscv_vfirst_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b8(op1,vl);
+}
+
+
+long test___riscv_vfirst_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b16(op1,vl);
+}
+
+
+long test___riscv_vfirst_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b32(op1,vl);
+}
+
+
+long test___riscv_vfirst_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b64(op1,vl);
+}
+
+
+long test___riscv_vfirst_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b1_m(mask,op1,vl);
+}
+
+
+long test___riscv_vfirst_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b2_m(mask,op1,vl);
+}
+
+
+long test___riscv_vfirst_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b4_m(mask,op1,vl);
+}
+
+
+long test___riscv_vfirst_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b8_m(mask,op1,vl);
+}
+
+
+long test___riscv_vfirst_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b16_m(mask,op1,vl);
+}
+
+
+long test___riscv_vfirst_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b32_m(mask,op1,vl);
+}
+
+
+long test___riscv_vfirst_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b64_m(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-2.c
new file mode 100644
index 00000000000..bd68d048aff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-2.c
@@ -0,0 +1,104 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+long test___riscv_vfirst_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b1(op1,31);
+}
+
+
+long test___riscv_vfirst_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b2(op1,31);
+}
+
+
+long test___riscv_vfirst_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b4(op1,31);
+}
+
+
+long test___riscv_vfirst_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b8(op1,31);
+}
+
+
+long test___riscv_vfirst_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b16(op1,31);
+}
+
+
+long test___riscv_vfirst_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b32(op1,31);
+}
+
+
+long test___riscv_vfirst_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b64(op1,31);
+}
+
+
+long test___riscv_vfirst_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b1_m(mask,op1,31);
+}
+
+
+long test___riscv_vfirst_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b2_m(mask,op1,31);
+}
+
+
+long test___riscv_vfirst_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b4_m(mask,op1,31);
+}
+
+
+long test___riscv_vfirst_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b8_m(mask,op1,31);
+}
+
+
+long test___riscv_vfirst_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b16_m(mask,op1,31);
+}
+
+
+long test___riscv_vfirst_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b32_m(mask,op1,31);
+}
+
+
+long test___riscv_vfirst_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b64_m(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-3.c
new file mode 100644
index 00000000000..641e4fa2982
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vfirst_m_m-3.c
@@ -0,0 +1,104 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+long test___riscv_vfirst_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b1(op1,32);
+}
+
+
+long test___riscv_vfirst_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b2(op1,32);
+}
+
+
+long test___riscv_vfirst_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b4(op1,32);
+}
+
+
+long test___riscv_vfirst_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b8(op1,32);
+}
+
+
+long test___riscv_vfirst_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b16(op1,32);
+}
+
+
+long test___riscv_vfirst_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b32(op1,32);
+}
+
+
+long test___riscv_vfirst_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b64(op1,32);
+}
+
+
+long test___riscv_vfirst_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b1_m(mask,op1,32);
+}
+
+
+long test___riscv_vfirst_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b2_m(mask,op1,32);
+}
+
+
+long test___riscv_vfirst_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b4_m(mask,op1,32);
+}
+
+
+long test___riscv_vfirst_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b8_m(mask,op1,32);
+}
+
+
+long test___riscv_vfirst_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b16_m(mask,op1,32);
+}
+
+
+long test___riscv_vfirst_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b32_m(mask,op1,32);
+}
+
+
+long test___riscv_vfirst_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vfirst_m_b64_m(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-1.c
new file mode 100644
index 00000000000..87f73b868c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-1.c
@@ -0,0 +1,55 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vlm_v_b1(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b1(base,vl);
+}
+
+
+vbool2_t test___riscv_vlm_v_b2(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b2(base,vl);
+}
+
+
+vbool4_t test___riscv_vlm_v_b4(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b4(base,vl);
+}
+
+
+vbool8_t test___riscv_vlm_v_b8(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b8(base,vl);
+}
+
+
+vbool16_t test___riscv_vlm_v_b16(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b16(base,vl);
+}
+
+
+vbool32_t test___riscv_vlm_v_b32(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b32(base,vl);
+}
+
+
+vbool64_t test___riscv_vlm_v_b64(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b64(base,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-2.c
new file mode 100644
index 00000000000..662ac7e4002
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-2.c
@@ -0,0 +1,55 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vlm_v_b1(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b1(base,31);
+}
+
+
+vbool2_t test___riscv_vlm_v_b2(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b2(base,31);
+}
+
+
+vbool4_t test___riscv_vlm_v_b4(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b4(base,31);
+}
+
+
+vbool8_t test___riscv_vlm_v_b8(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b8(base,31);
+}
+
+
+vbool16_t test___riscv_vlm_v_b16(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b16(base,31);
+}
+
+
+vbool32_t test___riscv_vlm_v_b32(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b32(base,31);
+}
+
+
+vbool64_t test___riscv_vlm_v_b64(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b64(base,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-3.c
new file mode 100644
index 00000000000..edac4f70a6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlm_v-3.c
@@ -0,0 +1,55 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vlm_v_b1(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b1(base,32);
+}
+
+
+vbool2_t test___riscv_vlm_v_b2(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b2(base,32);
+}
+
+
+vbool4_t test___riscv_vlm_v_b4(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b4(base,32);
+}
+
+
+vbool8_t test___riscv_vlm_v_b8(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b8(base,32);
+}
+
+
+vbool16_t test___riscv_vlm_v_b16(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b16(base,32);
+}
+
+
+vbool32_t test___riscv_vlm_v_b32(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b32(base,32);
+}
+
+
+vbool64_t test___riscv_vlm_v_b64(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b64(base,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-1.c
new file mode 100644
index 00000000000..ff158c86b23
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-1.c
@@ -0,0 +1,55 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void test___riscv_vsm_v_b1(uint8_t* base,vbool1_t value,size_t vl)
+{
+    __riscv_vsm_v_b1(base,value,vl);
+}
+
+
+void test___riscv_vsm_v_b2(uint8_t* base,vbool2_t value,size_t vl)
+{
+    __riscv_vsm_v_b2(base,value,vl);
+}
+
+
+void test___riscv_vsm_v_b4(uint8_t* base,vbool4_t value,size_t vl)
+{
+    __riscv_vsm_v_b4(base,value,vl);
+}
+
+
+void test___riscv_vsm_v_b8(uint8_t* base,vbool8_t value,size_t vl)
+{
+    __riscv_vsm_v_b8(base,value,vl);
+}
+
+
+void test___riscv_vsm_v_b16(uint8_t* base,vbool16_t value,size_t vl)
+{
+    __riscv_vsm_v_b16(base,value,vl);
+}
+
+
+void test___riscv_vsm_v_b32(uint8_t* base,vbool32_t value,size_t vl)
+{
+    __riscv_vsm_v_b32(base,value,vl);
+}
+
+
+void test___riscv_vsm_v_b64(uint8_t* base,vbool64_t value,size_t vl)
+{
+    __riscv_vsm_v_b64(base,value,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-2.c
new file mode 100644
index 00000000000..15a3575e3d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-2.c
@@ -0,0 +1,55 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void test___riscv_vsm_v_b1(uint8_t* base,vbool1_t value,size_t vl)
+{
+    __riscv_vsm_v_b1(base,value,31);
+}
+
+
+void test___riscv_vsm_v_b2(uint8_t* base,vbool2_t value,size_t vl)
+{
+    __riscv_vsm_v_b2(base,value,31);
+}
+
+
+void test___riscv_vsm_v_b4(uint8_t* base,vbool4_t value,size_t vl)
+{
+    __riscv_vsm_v_b4(base,value,31);
+}
+
+
+void test___riscv_vsm_v_b8(uint8_t* base,vbool8_t value,size_t vl)
+{
+    __riscv_vsm_v_b8(base,value,31);
+}
+
+
+void test___riscv_vsm_v_b16(uint8_t* base,vbool16_t value,size_t vl)
+{
+    __riscv_vsm_v_b16(base,value,31);
+}
+
+
+void test___riscv_vsm_v_b32(uint8_t* base,vbool32_t value,size_t vl)
+{
+    __riscv_vsm_v_b32(base,value,31);
+}
+
+
+void test___riscv_vsm_v_b64(uint8_t* base,vbool64_t value,size_t vl)
+{
+    __riscv_vsm_v_b64(base,value,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-3.c
new file mode 100644
index 00000000000..903303e166a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsm_v-3.c
@@ -0,0 +1,55 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void test___riscv_vsm_v_b1(uint8_t* base,vbool1_t value,size_t vl)
+{
+    __riscv_vsm_v_b1(base,value,32);
+}
+
+
+void test___riscv_vsm_v_b2(uint8_t* base,vbool2_t value,size_t vl)
+{
+    __riscv_vsm_v_b2(base,value,32);
+}
+
+
+void test___riscv_vsm_v_b4(uint8_t* base,vbool4_t value,size_t vl)
+{
+    __riscv_vsm_v_b4(base,value,32);
+}
+
+
+void test___riscv_vsm_v_b8(uint8_t* base,vbool8_t value,size_t vl)
+{
+    __riscv_vsm_v_b8(base,value,32);
+}
+
+
+void test___riscv_vsm_v_b16(uint8_t* base,vbool16_t value,size_t vl)
+{
+    __riscv_vsm_v_b16(base,value,32);
+}
+
+
+void test___riscv_vsm_v_b32(uint8_t* base,vbool32_t value,size_t vl)
+{
+    __riscv_vsm_v_b32(base,value,32);
+}
+
+
+void test___riscv_vsm_v_b64(uint8_t* base,vbool64_t value,size_t vl)
+{
+    __riscv_vsm_v_b64(base,value,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)} 1 } } */