diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-1.c
new file mode 100644
index 00000000000..9f11c8420dd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b1(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b2(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b4(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b8(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b16(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b32(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b64(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-2.c
new file mode 100644
index 00000000000..81d96b85f0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b1(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b2(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b4(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b8(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b16(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b32(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b64(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-3.c
new file mode 100644
index 00000000000..4b5dd50cf80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmand_mm-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b1(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b2(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b4(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b8(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b16(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b32(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmand_mm_b64(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-1.c
new file mode 100644
index 00000000000..f0ccd9f54f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmandn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b1(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmandn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b2(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmandn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b4(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmandn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b8(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmandn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b16(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmandn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b32(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmandn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b64(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-2.c
new file mode 100644
index 00000000000..a6605c4597d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmandn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b1(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmandn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b2(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmandn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b4(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmandn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b8(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmandn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b16(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmandn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b32(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmandn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b64(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-3.c
new file mode 100644
index 00000000000..ad48a8547b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmandn_mm-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmandn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b1(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmandn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b2(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmandn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b4(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmandn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b8(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmandn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b16(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmandn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b32(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmandn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmandn_mm_b64(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-1.c
new file mode 100644
index 00000000000..74f89f1a445
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmclr_m_b1(size_t vl)
+{
+    return __riscv_vmclr_m_b1(vl);
+}
+
+
+vbool2_t test___riscv_vmclr_m_b2(size_t vl)
+{
+    return __riscv_vmclr_m_b2(vl);
+}
+
+
+vbool4_t test___riscv_vmclr_m_b4(size_t vl)
+{
+    return __riscv_vmclr_m_b4(vl);
+}
+
+
+vbool8_t test___riscv_vmclr_m_b8(size_t vl)
+{
+    return __riscv_vmclr_m_b8(vl);
+}
+
+
+vbool16_t test___riscv_vmclr_m_b16(size_t vl)
+{
+    return __riscv_vmclr_m_b16(vl);
+}
+
+
+vbool32_t test___riscv_vmclr_m_b32(size_t vl)
+{
+    return __riscv_vmclr_m_b32(vl);
+}
+
+
+vbool64_t test___riscv_vmclr_m_b64(size_t vl)
+{
+    return __riscv_vmclr_m_b64(vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-2.c
new file mode 100644
index 00000000000..e4c91959dd3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmclr_m_b1(size_t vl)
+{
+    return __riscv_vmclr_m_b1(31);
+}
+
+
+vbool2_t test___riscv_vmclr_m_b2(size_t vl)
+{
+    return __riscv_vmclr_m_b2(31);
+}
+
+
+vbool4_t test___riscv_vmclr_m_b4(size_t vl)
+{
+    return __riscv_vmclr_m_b4(31);
+}
+
+
+vbool8_t test___riscv_vmclr_m_b8(size_t vl)
+{
+    return __riscv_vmclr_m_b8(31);
+}
+
+
+vbool16_t test___riscv_vmclr_m_b16(size_t vl)
+{
+    return __riscv_vmclr_m_b16(31);
+}
+
+
+vbool32_t test___riscv_vmclr_m_b32(size_t vl)
+{
+    return __riscv_vmclr_m_b32(31);
+}
+
+
+vbool64_t test___riscv_vmclr_m_b64(size_t vl)
+{
+    return __riscv_vmclr_m_b64(31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-3.c
new file mode 100644
index 00000000000..12cd1a5c0fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmclr_m_m-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmclr_m_b1(size_t vl)
+{
+    return __riscv_vmclr_m_b1(32);
+}
+
+
+vbool2_t test___riscv_vmclr_m_b2(size_t vl)
+{
+    return __riscv_vmclr_m_b2(32);
+}
+
+
+vbool4_t test___riscv_vmclr_m_b4(size_t vl)
+{
+    return __riscv_vmclr_m_b4(32);
+}
+
+
+vbool8_t test___riscv_vmclr_m_b8(size_t vl)
+{
+    return __riscv_vmclr_m_b8(32);
+}
+
+
+vbool16_t test___riscv_vmclr_m_b16(size_t vl)
+{
+    return __riscv_vmclr_m_b16(32);
+}
+
+
+vbool32_t test___riscv_vmclr_m_b32(size_t vl)
+{
+    return __riscv_vmclr_m_b32(32);
+}
+
+
+vbool64_t test___riscv_vmclr_m_b64(size_t vl)
+{
+    return __riscv_vmclr_m_b64(32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-1.c
new file mode 100644
index 00000000000..8ebb69128b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmmv_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b1(op1,vl);
+}
+
+
+vbool2_t test___riscv_vmmv_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b2(op1,vl);
+}
+
+
+vbool4_t test___riscv_vmmv_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b4(op1,vl);
+}
+
+
+vbool8_t test___riscv_vmmv_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b8(op1,vl);
+}
+
+
+vbool16_t test___riscv_vmmv_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b16(op1,vl);
+}
+
+
+vbool32_t test___riscv_vmmv_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b32(op1,vl);
+}
+
+
+vbool64_t test___riscv_vmmv_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b64(op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-2.c
new file mode 100644
index 00000000000..bd97c0daa7e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmmv_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b1(op1,31);
+}
+
+
+vbool2_t test___riscv_vmmv_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b2(op1,31);
+}
+
+
+vbool4_t test___riscv_vmmv_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b4(op1,31);
+}
+
+
+vbool8_t test___riscv_vmmv_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b8(op1,31);
+}
+
+
+vbool16_t test___riscv_vmmv_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b16(op1,31);
+}
+
+
+vbool32_t test___riscv_vmmv_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b32(op1,31);
+}
+
+
+vbool64_t test___riscv_vmmv_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b64(op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-3.c
new file mode 100644
index 00000000000..fa8cb2f6f6f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmmv_m_m-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmmv_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b1(op1,32);
+}
+
+
+vbool2_t test___riscv_vmmv_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b2(op1,32);
+}
+
+
+vbool4_t test___riscv_vmmv_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b4(op1,32);
+}
+
+
+vbool8_t test___riscv_vmmv_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b8(op1,32);
+}
+
+
+vbool16_t test___riscv_vmmv_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b16(op1,32);
+}
+
+
+vbool32_t test___riscv_vmmv_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b32(op1,32);
+}
+
+
+vbool64_t test___riscv_vmmv_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vmmv_m_b64(op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-1.c
new file mode 100644
index 00000000000..9c2f38f6194
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b1(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmnand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b2(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmnand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b4(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmnand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b8(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmnand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b16(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmnand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b32(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmnand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b64(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-2.c
new file mode 100644
index 00000000000..35eeedb12e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b1(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmnand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b2(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmnand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b4(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmnand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b8(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmnand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b16(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmnand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b32(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmnand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b64(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-3.c
new file mode 100644
index 00000000000..69b32ef8111
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnand_mm-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnand_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b1(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmnand_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b2(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmnand_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b4(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmnand_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b8(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmnand_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b16(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmnand_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b32(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmnand_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmnand_mm_b64(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-1.c
new file mode 100644
index 00000000000..7724fcb2725
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b1(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b2(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b4(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b8(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b16(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b32(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b64(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-2.c
new file mode 100644
index 00000000000..91eabb9a800
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b1(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b2(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b4(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b8(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b16(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b32(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b64(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-3.c
new file mode 100644
index 00000000000..2eb333b6f46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnor_mm-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b1(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b2(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b4(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b8(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b16(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b32(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmnor_mm_b64(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-1.c
new file mode 100644
index 00000000000..bba5506cf11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnot_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b1(op1,vl);
+}
+
+
+vbool2_t test___riscv_vmnot_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b2(op1,vl);
+}
+
+
+vbool4_t test___riscv_vmnot_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b4(op1,vl);
+}
+
+
+vbool8_t test___riscv_vmnot_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b8(op1,vl);
+}
+
+
+vbool16_t test___riscv_vmnot_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b16(op1,vl);
+}
+
+
+vbool32_t test___riscv_vmnot_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b32(op1,vl);
+}
+
+
+vbool64_t test___riscv_vmnot_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b64(op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-2.c
new file mode 100644
index 00000000000..a7c872372a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnot_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b1(op1,31);
+}
+
+
+vbool2_t test___riscv_vmnot_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b2(op1,31);
+}
+
+
+vbool4_t test___riscv_vmnot_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b4(op1,31);
+}
+
+
+vbool8_t test___riscv_vmnot_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b8(op1,31);
+}
+
+
+vbool16_t test___riscv_vmnot_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b16(op1,31);
+}
+
+
+vbool32_t test___riscv_vmnot_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b32(op1,31);
+}
+
+
+vbool64_t test___riscv_vmnot_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b64(op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-3.c
new file mode 100644
index 00000000000..8c68be9f870
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmnot_m_m-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmnot_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b1(op1,32);
+}
+
+
+vbool2_t test___riscv_vmnot_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b2(op1,32);
+}
+
+
+vbool4_t test___riscv_vmnot_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b4(op1,32);
+}
+
+
+vbool8_t test___riscv_vmnot_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b8(op1,32);
+}
+
+
+vbool16_t test___riscv_vmnot_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b16(op1,32);
+}
+
+
+vbool32_t test___riscv_vmnot_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b32(op1,32);
+}
+
+
+vbool64_t test___riscv_vmnot_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vmnot_m_b64(op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-1.c
new file mode 100644
index 00000000000..638c0b3743f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b1(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b2(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b4(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b8(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b16(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b32(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b64(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-2.c
new file mode 100644
index 00000000000..eb8ebc25904
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b1(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b2(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b4(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b8(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b16(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b32(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b64(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-3.c
new file mode 100644
index 00000000000..3b6a7e81ef9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmor_mm-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b1(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b2(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b4(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b8(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b16(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b32(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmor_mm_b64(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-1.c
new file mode 100644
index 00000000000..c8c383dbc78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmorn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b1(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmorn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b2(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmorn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b4(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmorn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b8(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmorn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b16(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmorn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b32(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmorn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b64(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-2.c
new file mode 100644
index 00000000000..d612293066c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmorn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b1(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmorn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b2(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmorn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b4(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmorn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b8(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmorn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b16(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmorn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b32(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmorn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b64(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-3.c
new file mode 100644
index 00000000000..d3701ddc453
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmorn_mm-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmorn_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b1(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmorn_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b2(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmorn_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b4(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmorn_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b8(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmorn_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b16(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmorn_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b32(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmorn_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmorn_mm_b64(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-1.c
new file mode 100644
index 00000000000..393928d7069
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsbf_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b1(op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b2(op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b4(op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b8(op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b16(op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b32(op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b64(op1,vl);
+}
+
+
+vbool1_t test___riscv_vmsbf_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b1_m(mask,op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b2_m(mask,op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b4_m(mask,op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b8_m(mask,op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b16_m(mask,op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b32_m(mask,op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b64_m(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-2.c
new file mode 100644
index 00000000000..961282f52a4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-2.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsbf_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b1(op1,31);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b2(op1,31);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b4(op1,31);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b8(op1,31);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b16(op1,31);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b32(op1,31);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b64(op1,31);
+}
+
+
+vbool1_t test___riscv_vmsbf_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b1_m(mask,op1,31);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b2_m(mask,op1,31);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b4_m(mask,op1,31);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b8_m(mask,op1,31);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b16_m(mask,op1,31);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b32_m(mask,op1,31);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b64_m(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-3.c
new file mode 100644
index 00000000000..60802fa81d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_m-3.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsbf_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b1(op1,32);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b2(op1,32);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b4(op1,32);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b8(op1,32);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b16(op1,32);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b32(op1,32);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b64(op1,32);
+}
+
+
+vbool1_t test___riscv_vmsbf_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b1_m(mask,op1,32);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b2_m(mask,op1,32);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b4_m(mask,op1,32);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b8_m(mask,op1,32);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b16_m(mask,op1,32);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b32_m(mask,op1,32);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b64_m(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c
new file mode 100644
index 00000000000..81255e48b63
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsbf_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b1_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b2_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b4_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b8_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b16_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b32_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b64_mu(mask,maskedoff,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c
new file mode 100644
index 00000000000..377613d89af
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsbf_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b1_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b2_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b4_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b8_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b16_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b32_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b64_mu(mask,maskedoff,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c
new file mode 100644
index 00000000000..16ebb27f67c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsbf_m_mu-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsbf_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b1_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool2_t test___riscv_vmsbf_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b2_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool4_t test___riscv_vmsbf_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b4_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool8_t test___riscv_vmsbf_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b8_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool16_t test___riscv_vmsbf_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b16_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool32_t test___riscv_vmsbf_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b32_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool64_t test___riscv_vmsbf_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsbf_m_b64_mu(mask,maskedoff,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-1.c
new file mode 100644
index 00000000000..3be6e704197
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmset_m_b1(size_t vl)
+{
+    return __riscv_vmset_m_b1(vl);
+}
+
+
+vbool2_t test___riscv_vmset_m_b2(size_t vl)
+{
+    return __riscv_vmset_m_b2(vl);
+}
+
+
+vbool4_t test___riscv_vmset_m_b4(size_t vl)
+{
+    return __riscv_vmset_m_b4(vl);
+}
+
+
+vbool8_t test___riscv_vmset_m_b8(size_t vl)
+{
+    return __riscv_vmset_m_b8(vl);
+}
+
+
+vbool16_t test___riscv_vmset_m_b16(size_t vl)
+{
+    return __riscv_vmset_m_b16(vl);
+}
+
+
+vbool32_t test___riscv_vmset_m_b32(size_t vl)
+{
+    return __riscv_vmset_m_b32(vl);
+}
+
+
+vbool64_t test___riscv_vmset_m_b64(size_t vl)
+{
+    return __riscv_vmset_m_b64(vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-2.c
new file mode 100644
index 00000000000..d020c8decaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmset_m_b1(size_t vl)
+{
+    return __riscv_vmset_m_b1(31);
+}
+
+
+vbool2_t test___riscv_vmset_m_b2(size_t vl)
+{
+    return __riscv_vmset_m_b2(31);
+}
+
+
+vbool4_t test___riscv_vmset_m_b4(size_t vl)
+{
+    return __riscv_vmset_m_b4(31);
+}
+
+
+vbool8_t test___riscv_vmset_m_b8(size_t vl)
+{
+    return __riscv_vmset_m_b8(31);
+}
+
+
+vbool16_t test___riscv_vmset_m_b16(size_t vl)
+{
+    return __riscv_vmset_m_b16(31);
+}
+
+
+vbool32_t test___riscv_vmset_m_b32(size_t vl)
+{
+    return __riscv_vmset_m_b32(31);
+}
+
+
+vbool64_t test___riscv_vmset_m_b64(size_t vl)
+{
+    return __riscv_vmset_m_b64(31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-3.c
new file mode 100644
index 00000000000..e1761956b0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmset_m_m-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmset_m_b1(size_t vl)
+{
+    return __riscv_vmset_m_b1(32);
+}
+
+
+vbool2_t test___riscv_vmset_m_b2(size_t vl)
+{
+    return __riscv_vmset_m_b2(32);
+}
+
+
+vbool4_t test___riscv_vmset_m_b4(size_t vl)
+{
+    return __riscv_vmset_m_b4(32);
+}
+
+
+vbool8_t test___riscv_vmset_m_b8(size_t vl)
+{
+    return __riscv_vmset_m_b8(32);
+}
+
+
+vbool16_t test___riscv_vmset_m_b16(size_t vl)
+{
+    return __riscv_vmset_m_b16(32);
+}
+
+
+vbool32_t test___riscv_vmset_m_b32(size_t vl)
+{
+    return __riscv_vmset_m_b32(32);
+}
+
+
+vbool64_t test___riscv_vmset_m_b64(size_t vl)
+{
+    return __riscv_vmset_m_b64(32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-1.c
new file mode 100644
index 00000000000..e22e1772c92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsif_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b1(op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b2(op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b4(op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b8(op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b16(op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b32(op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b64(op1,vl);
+}
+
+
+vbool1_t test___riscv_vmsif_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b1_m(mask,op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b2_m(mask,op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b4_m(mask,op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b8_m(mask,op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b16_m(mask,op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b32_m(mask,op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b64_m(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-2.c
new file mode 100644
index 00000000000..cb7ad9faece
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-2.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsif_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b1(op1,31);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b2(op1,31);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b4(op1,31);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b8(op1,31);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b16(op1,31);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b32(op1,31);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b64(op1,31);
+}
+
+
+vbool1_t test___riscv_vmsif_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b1_m(mask,op1,31);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b2_m(mask,op1,31);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b4_m(mask,op1,31);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b8_m(mask,op1,31);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b16_m(mask,op1,31);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b32_m(mask,op1,31);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b64_m(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-3.c
new file mode 100644
index 00000000000..c92b0e9b89a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_m-3.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsif_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b1(op1,32);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b2(op1,32);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b4(op1,32);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b8(op1,32);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b16(op1,32);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b32(op1,32);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b64(op1,32);
+}
+
+
+vbool1_t test___riscv_vmsif_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b1_m(mask,op1,32);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b2_m(mask,op1,32);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b4_m(mask,op1,32);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b8_m(mask,op1,32);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b16_m(mask,op1,32);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b32_m(mask,op1,32);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b64_m(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-1.c
new file mode 100644
index 00000000000..7a7075e61e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsif_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b1_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b2_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b4_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b8_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b16_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b32_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b64_mu(mask,maskedoff,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-2.c
new file mode 100644
index 00000000000..8e8222bd3b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsif_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b1_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b2_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b4_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b8_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b16_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b32_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b64_mu(mask,maskedoff,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-3.c
new file mode 100644
index 00000000000..c305562df82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsif_m_mu-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsif_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b1_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool2_t test___riscv_vmsif_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b2_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool4_t test___riscv_vmsif_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b4_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool8_t test___riscv_vmsif_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b8_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool16_t test___riscv_vmsif_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b16_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool32_t test___riscv_vmsif_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b32_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool64_t test___riscv_vmsif_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsif_m_b64_mu(mask,maskedoff,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-1.c
new file mode 100644
index 00000000000..87202ff62ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-1.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsof_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b1(op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b2(op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b4(op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b8(op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b16(op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b32(op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b64(op1,vl);
+}
+
+
+vbool1_t test___riscv_vmsof_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b1_m(mask,op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b2_m(mask,op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b4_m(mask,op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b8_m(mask,op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b16_m(mask,op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b32_m(mask,op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b64_m(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-2.c
new file mode 100644
index 00000000000..6e4f3ce1288
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-2.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsof_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b1(op1,31);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b2(op1,31);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b4(op1,31);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b8(op1,31);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b16(op1,31);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b32(op1,31);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b64(op1,31);
+}
+
+
+vbool1_t test___riscv_vmsof_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b1_m(mask,op1,31);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b2_m(mask,op1,31);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b4_m(mask,op1,31);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b8_m(mask,op1,31);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b16_m(mask,op1,31);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b32_m(mask,op1,31);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b64_m(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-3.c
new file mode 100644
index 00000000000..55cf50d5c9d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_m-3.c
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsof_m_b1(vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b1(op1,32);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2(vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b2(op1,32);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4(vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b4(op1,32);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8(vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b8(op1,32);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16(vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b16(op1,32);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32(vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b32(op1,32);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64(vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b64(op1,32);
+}
+
+
+vbool1_t test___riscv_vmsof_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b1_m(mask,op1,32);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b2_m(mask,op1,32);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b4_m(mask,op1,32);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b8_m(mask,op1,32);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b16_m(mask,op1,32);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b32_m(mask,op1,32);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b64_m(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-1.c
new file mode 100644
index 00000000000..4b9d846631e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsof_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b1_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b2_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b4_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b8_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b16_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b32_mu(mask,maskedoff,op1,vl);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b64_mu(mask,maskedoff,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-2.c
new file mode 100644
index 00000000000..3f4ea728505
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsof_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b1_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b2_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b4_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b8_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b16_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b32_mu(mask,maskedoff,op1,31);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b64_mu(mask,maskedoff,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-3.c
new file mode 100644
index 00000000000..9c143bfc746
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsof_m_mu-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmsof_m_b1_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b1_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool2_t test___riscv_vmsof_m_b2_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b2_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool4_t test___riscv_vmsof_m_b4_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b4_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool8_t test___riscv_vmsof_m_b8_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b8_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool16_t test___riscv_vmsof_m_b16_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b16_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool32_t test___riscv_vmsof_m_b32_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b32_mu(mask,maskedoff,op1,32);
+}
+
+
+vbool64_t test___riscv_vmsof_m_b64_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_vmsof_m_b64_mu(mask,maskedoff,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-1.c
new file mode 100644
index 00000000000..0d63ea7718e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmxnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b1(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmxnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b2(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmxnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b4(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmxnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b8(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmxnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b16(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmxnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b32(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmxnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b64(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-2.c
new file mode 100644
index 00000000000..ba39230b2b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmxnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b1(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmxnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b2(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmxnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b4(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmxnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b8(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmxnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b16(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmxnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b32(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmxnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b64(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-3.c
new file mode 100644
index 00000000000..e74c39b5dde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxnor_mm-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmxnor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b1(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmxnor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b2(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmxnor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b4(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmxnor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b8(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmxnor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b16(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmxnor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b32(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmxnor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmxnor_mm_b64(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-1.c
new file mode 100644
index 00000000000..b7072e492fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-1.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmxor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b1(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmxor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b2(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmxor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b4(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmxor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b8(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmxor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b16(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmxor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b32(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmxor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b64(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-2.c
new file mode 100644
index 00000000000..3222cd2f7bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-2.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmxor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b1(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmxor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b2(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmxor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b4(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmxor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b8(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmxor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b16(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmxor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b32(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmxor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b64(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-3.c
new file mode 100644
index 00000000000..9938dc94151
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmxor_mm-3.c
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vmxor_mm_b1(vbool1_t op1,vbool1_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b1(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmxor_mm_b2(vbool2_t op1,vbool2_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b2(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmxor_mm_b4(vbool4_t op1,vbool4_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b4(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmxor_mm_b8(vbool8_t op1,vbool8_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b8(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmxor_mm_b16(vbool16_t op1,vbool16_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b16(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmxor_mm_b32(vbool32_t op1,vbool32_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b32(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmxor_mm_b64(vbool64_t op1,vbool64_t op2,size_t vl)
+{
+    return __riscv_vmxor_mm_b64(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
