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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id gj29-20020a170907741d00b008b13599a4b8si1022498ejc.748.2023.02.14.07.39.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Feb 2023 07:39:43 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B21B93858430 for ; Tue, 14 Feb 2023 15:39:39 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id 85D583858D33 for ; Tue, 14 Feb 2023 15:39:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 85D583858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp80t1676389145t7810mdg Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 14 Feb 2023 23:39:04 +0800 (CST) X-QQ-SSF: 00400000002000E0L000B00A0000000 X-QQ-FEAT: 239gR2IZrltVCeuDaaZjXfO67eB2FJ4FFBVh14Vy24LyjJdLcMFy1KkmRrNbx /IdfLoFY9uY0JG18PDzt1LH+cw96PuP2zFcD4jWaOI65mPnMMvJQkAKkC08UCOHIQBWRzm3 f0jiWMiN/bHrPOI2cz5aNCDfDDOHUccIDVxxdIQ49rSNTT/IAcY1dzG4VyvwqH3l9Gd1bsc 6Q54Vw9e0lq5tGQ8QVRLBKDGucMUPX4hVI0YECR2p0b3EAbrlzGPlcfg4AqWnxVOmhzYAK5 WFlz02uXBywOmpoYtGhKgTzXyVQHngO+VjhV+XBdy064i0pnbfINtxl6VBQSrPBYSAKs37O /lS81rezETekK6hDOroUX761oqFUQEoWJedfmL5Od7PTnvQs1GGXn9N0ezP7XPEU9ULxPTV X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] =?utf-8?q?RISC-V=3A_Remove_=22extern=E2=80=9C_for_namespace?= [NFC] Date: Tue, 14 Feb 2023 23:39:03 +0800 Message-Id: <20230214153903.27974-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757821464556951348?= X-GMAIL-MSGID: =?utf-8?q?1757821464556951348?= From: Ju-Zhe Zhong Just like other targets, aarch64_sve namespace in aarch64-protos.h arm_mve in arm-protos, nds namesace in nds32-protos.h They all don't have 'extern' in namespace. This is a NFC patch to make RISC-V be consistent with other targets. No functionality change. gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_run_selftests): Remove 'extern'. (init_builtins): Ditto. (mangle_builtin_type): Ditto. (verify_type_context): Ditto. (handle_pragma_vector): Ditto. (builtin_decl): Ditto. (expand_builtin): Ditto. (const_vec_all_same_in_range_p): Ditto. (legitimize_move): Ditto. (emit_vlmax_op): Ditto. (emit_nonvlmax_op): Ditto. (get_vlmul): Ditto. (get_ratio): Ditto. (get_ta): Ditto. (get_ma): Ditto. (get_avl_type): Ditto. (calculate_ratio): Ditto. (enum vlmul_type): Ditto. (simm5_p): Ditto. (neg_simm5_p): Ditto. (has_vi_variant_p): Ditto. --- gcc/config/riscv/riscv-protos.h | 40 ++++++++++++++++----------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index ee8e903ddf5..81ad2eabc00 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -115,7 +115,7 @@ extern const riscv_cpu_info *riscv_find_cpu (const char *); /* Routines implemented in riscv-selftests.cc. */ #if CHECKING_P namespace selftest { -extern void riscv_run_selftests (void); +void riscv_run_selftests (void); } // namespace selftest #endif @@ -141,24 +141,24 @@ enum avl_type VLMAX, }; /* Routines implemented in riscv-vector-builtins.cc. */ -extern void init_builtins (void); -extern const char *mangle_builtin_type (const_tree); +void init_builtins (void); +const char *mangle_builtin_type (const_tree); #ifdef GCC_TARGET_H -extern bool verify_type_context (location_t, type_context_kind, const_tree, bool); +bool verify_type_context (location_t, type_context_kind, const_tree, bool); #endif -extern void handle_pragma_vector (void); -extern tree builtin_decl (unsigned, bool); -extern rtx expand_builtin (unsigned int, tree, rtx); -extern bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT); -extern bool legitimize_move (rtx, rtx, machine_mode); -extern void emit_vlmax_op (unsigned, rtx, rtx, machine_mode); -extern void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode); -extern enum vlmul_type get_vlmul (machine_mode); -extern unsigned int get_ratio (machine_mode); -extern int get_ta (rtx); -extern int get_ma (rtx); -extern int get_avl_type (rtx); -extern unsigned int calculate_ratio (unsigned int, enum vlmul_type); +void handle_pragma_vector (void); +tree builtin_decl (unsigned, bool); +rtx expand_builtin (unsigned int, tree, rtx); +bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT); +bool legitimize_move (rtx, rtx, machine_mode); +void emit_vlmax_op (unsigned, rtx, rtx, machine_mode); +void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode); +enum vlmul_type get_vlmul (machine_mode); +unsigned int get_ratio (machine_mode); +int get_ta (rtx); +int get_ma (rtx); +int get_avl_type (rtx); +unsigned int calculate_ratio (unsigned int, enum vlmul_type); enum tail_policy { TAIL_UNDISTURBED = 0, @@ -176,10 +176,10 @@ enum tail_policy get_prefer_tail_policy (); enum mask_policy get_prefer_mask_policy (); rtx get_avl_type_rtx (enum avl_type); opt_machine_mode get_vector_mode (scalar_mode, poly_uint64); -extern bool simm5_p (rtx); -extern bool neg_simm5_p (rtx); +bool simm5_p (rtx); +bool neg_simm5_p (rtx); #ifdef RTX_CODE -extern bool has_vi_variant_p (rtx_code, rtx); +bool has_vi_variant_p (rtx_code, rtx); #endif }