diff mbox series

RISC-V: Add vmacc vv c++ api tests

Message ID 20230214143259.155429-1-juzhe.zhong@rivai.ai
State Accepted
Headers
Series RISC-V: Add vmacc vv c++ api tests |

Checks

Context Check Description
snail/gcc-patch-check success Github commit url

Commit Message

juzhe.zhong@rivai.ai Feb. 14, 2023, 2:32 p.m. UTC 
  From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vmacc_vv-1.C: New test.
        * g++.target/riscv/rvv/base/vmacc_vv-2.C: New test.
        * g++.target/riscv/rvv/base/vmacc_vv-3.C: New test.
        * g++.target/riscv/rvv/base/vmacc_vv_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vmacc_vv_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vmacc_vv_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vmacc_vv_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vmacc_vv_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vmacc_vv_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vmacc_vv_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vmacc_vv_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vmacc_vv_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vmacc_vv_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vmacc_vv_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vmacc_vv_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vmacc_vv-1.C    | 578 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmacc_vv-2.C    | 578 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmacc_vv-3.C    | 578 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vmacc_vv_mu-1.C | 292 +++++++++
 .../g++.target/riscv/rvv/base/vmacc_vv_mu-2.C | 292 +++++++++
 .../g++.target/riscv/rvv/base/vmacc_vv_mu-3.C | 292 +++++++++
 .../g++.target/riscv/rvv/base/vmacc_vv_tu-1.C | 292 +++++++++
 .../g++.target/riscv/rvv/base/vmacc_vv_tu-2.C | 292 +++++++++
 .../g++.target/riscv/rvv/base/vmacc_vv_tu-3.C | 292 +++++++++
 .../riscv/rvv/base/vmacc_vv_tum-1.C           | 292 +++++++++
 .../riscv/rvv/base/vmacc_vv_tum-2.C           | 292 +++++++++
 .../riscv/rvv/base/vmacc_vv_tum-3.C           | 292 +++++++++
 .../riscv/rvv/base/vmacc_vv_tumu-1.C          | 292 +++++++++
 .../riscv/rvv/base/vmacc_vv_tumu-2.C          | 292 +++++++++
 .../riscv/rvv/base/vmacc_vv_tumu-3.C          | 292 +++++++++
 15 files changed, 5238 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-3.C
diff mbox series

Patch

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-1.C
new file mode 100644
index 00000000000..1fca6041842
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-1.C
@@ -0,0 +1,578 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmacc(vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmacc(vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmacc(vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vmacc(vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vmacc(vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vmacc(vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vmacc(vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmacc(vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmacc(vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vmacc(vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vmacc(vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vmacc(vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vmacc(vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmacc(vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vmacc(vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vmacc(vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vmacc(vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vmacc(vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vmacc(vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vmacc(vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vmacc(vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vmacc(vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmacc(vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmacc(vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmacc(vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vmacc(vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vmacc(vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vmacc(vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vmacc(vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vmacc(vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vmacc(vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vmacc(vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vmacc(vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vmacc(vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vmacc(vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vmacc(vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vmacc(vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vmacc(vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vmacc(vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vmacc(vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vmacc(vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vmacc(vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vmacc(vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vmacc(vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,vl);
+}
+
+
+vint8mf8_t test___riscv_vmacc(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmacc(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmacc(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vmacc(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vmacc(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vmacc(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vmacc(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmacc(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmacc(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vmacc(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vmacc(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vmacc(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vmacc(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmacc(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vmacc(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vmacc(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vmacc(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vmacc(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vmacc(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vmacc(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vmacc(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vmacc(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmacc(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmacc(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmacc(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vmacc(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vmacc(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vmacc(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vmacc(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vmacc(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vmacc(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vmacc(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vmacc(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vmacc(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vmacc(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vmacc(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vmacc(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vmacc(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vmacc(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vmacc(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vmacc(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vmacc(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vmacc(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vmacc(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-2.C
new file mode 100644
index 00000000000..1b202a26168
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-2.C
@@ -0,0 +1,578 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmacc(vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vmacc(vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vmacc(vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vmacc(vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vmacc(vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vmacc(vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vmacc(vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vmacc(vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vmacc(vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vmacc(vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vmacc(vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vmacc(vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vmacc(vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vmacc(vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vmacc(vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vmacc(vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vmacc(vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vmacc(vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vmacc(vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vmacc(vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vmacc(vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vmacc(vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vmacc(vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vmacc(vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vmacc(vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vmacc(vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vmacc(vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vmacc(vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vmacc(vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vmacc(vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vmacc(vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vmacc(vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vmacc(vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vmacc(vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vmacc(vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vmacc(vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vmacc(vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vmacc(vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vmacc(vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vmacc(vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vmacc(vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vmacc(vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vmacc(vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vmacc(vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,31);
+}
+
+
+vint8mf8_t test___riscv_vmacc(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vmacc(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vmacc(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vmacc(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vmacc(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vmacc(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vmacc(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vmacc(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vmacc(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vmacc(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vmacc(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vmacc(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vmacc(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vmacc(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vmacc(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vmacc(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vmacc(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vmacc(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vmacc(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vmacc(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vmacc(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vmacc(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vmacc(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vmacc(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vmacc(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vmacc(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vmacc(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vmacc(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vmacc(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vmacc(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vmacc(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vmacc(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vmacc(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vmacc(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vmacc(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vmacc(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vmacc(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vmacc(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vmacc(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vmacc(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vmacc(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vmacc(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vmacc(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vmacc(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-3.C
new file mode 100644
index 00000000000..a87006a2534
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-3.C
@@ -0,0 +1,578 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmacc(vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vmacc(vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vmacc(vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vmacc(vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vmacc(vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vmacc(vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vmacc(vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vmacc(vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vmacc(vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vmacc(vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vmacc(vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vmacc(vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vmacc(vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vmacc(vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vmacc(vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vmacc(vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vmacc(vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vmacc(vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vmacc(vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vmacc(vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vmacc(vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vmacc(vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vmacc(vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vmacc(vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vmacc(vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vmacc(vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vmacc(vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vmacc(vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vmacc(vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vmacc(vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vmacc(vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vmacc(vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vmacc(vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vmacc(vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vmacc(vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vmacc(vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vmacc(vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vmacc(vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vmacc(vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vmacc(vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vmacc(vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vmacc(vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vmacc(vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vmacc(vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(vd,vs1,vs2,32);
+}
+
+
+vint8mf8_t test___riscv_vmacc(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vmacc(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vmacc(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vmacc(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vmacc(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vmacc(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vmacc(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vmacc(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vmacc(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vmacc(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vmacc(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vmacc(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vmacc(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vmacc(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vmacc(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vmacc(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vmacc(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vmacc(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vmacc(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vmacc(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vmacc(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vmacc(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vmacc(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vmacc(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vmacc(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vmacc(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vmacc(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vmacc(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vmacc(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vmacc(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vmacc(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vmacc(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vmacc(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vmacc(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vmacc(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vmacc(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vmacc(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vmacc(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vmacc(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vmacc(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vmacc(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vmacc(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vmacc(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vmacc(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-1.C
new file mode 100644
index 00000000000..0dbc6b8bb87
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-1.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmacc_mu(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmacc_mu(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmacc_mu(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vmacc_mu(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vmacc_mu(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vmacc_mu(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vmacc_mu(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmacc_mu(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmacc_mu(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vmacc_mu(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vmacc_mu(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vmacc_mu(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vmacc_mu(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmacc_mu(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vmacc_mu(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vmacc_mu(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vmacc_mu(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vmacc_mu(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vmacc_mu(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vmacc_mu(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vmacc_mu(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vmacc_mu(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmacc_mu(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmacc_mu(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmacc_mu(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vmacc_mu(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vmacc_mu(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vmacc_mu(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vmacc_mu(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vmacc_mu(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vmacc_mu(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vmacc_mu(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vmacc_mu(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vmacc_mu(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vmacc_mu(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vmacc_mu(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vmacc_mu(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vmacc_mu(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vmacc_mu(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vmacc_mu(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vmacc_mu(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vmacc_mu(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vmacc_mu(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vmacc_mu(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-2.C
new file mode 100644
index 00000000000..164475791f8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-2.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmacc_mu(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vmacc_mu(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vmacc_mu(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vmacc_mu(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vmacc_mu(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vmacc_mu(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vmacc_mu(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vmacc_mu(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vmacc_mu(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vmacc_mu(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vmacc_mu(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vmacc_mu(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vmacc_mu(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vmacc_mu(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vmacc_mu(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vmacc_mu(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vmacc_mu(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vmacc_mu(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vmacc_mu(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vmacc_mu(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vmacc_mu(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vmacc_mu(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vmacc_mu(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vmacc_mu(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vmacc_mu(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vmacc_mu(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vmacc_mu(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vmacc_mu(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vmacc_mu(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vmacc_mu(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vmacc_mu(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vmacc_mu(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vmacc_mu(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vmacc_mu(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vmacc_mu(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vmacc_mu(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vmacc_mu(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vmacc_mu(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vmacc_mu(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vmacc_mu(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vmacc_mu(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vmacc_mu(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vmacc_mu(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vmacc_mu(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-3.C
new file mode 100644
index 00000000000..946c574628c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-3.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmacc_mu(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vmacc_mu(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vmacc_mu(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vmacc_mu(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vmacc_mu(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vmacc_mu(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vmacc_mu(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vmacc_mu(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vmacc_mu(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vmacc_mu(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vmacc_mu(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vmacc_mu(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vmacc_mu(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vmacc_mu(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vmacc_mu(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vmacc_mu(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vmacc_mu(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vmacc_mu(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vmacc_mu(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vmacc_mu(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vmacc_mu(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vmacc_mu(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vmacc_mu(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vmacc_mu(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vmacc_mu(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vmacc_mu(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vmacc_mu(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vmacc_mu(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vmacc_mu(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vmacc_mu(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vmacc_mu(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vmacc_mu(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vmacc_mu(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vmacc_mu(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vmacc_mu(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vmacc_mu(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vmacc_mu(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vmacc_mu(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vmacc_mu(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vmacc_mu(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vmacc_mu(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vmacc_mu(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vmacc_mu(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vmacc_mu(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_mu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-1.C
new file mode 100644
index 00000000000..c4b2ad39f0b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-1.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmacc_tu(vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmacc_tu(vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmacc_tu(vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vmacc_tu(vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vmacc_tu(vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vmacc_tu(vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vmacc_tu(vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmacc_tu(vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmacc_tu(vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vmacc_tu(vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vmacc_tu(vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vmacc_tu(vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vmacc_tu(vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmacc_tu(vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vmacc_tu(vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vmacc_tu(vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vmacc_tu(vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vmacc_tu(vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vmacc_tu(vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vmacc_tu(vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vmacc_tu(vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vmacc_tu(vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmacc_tu(vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmacc_tu(vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmacc_tu(vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vmacc_tu(vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vmacc_tu(vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vmacc_tu(vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vmacc_tu(vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vmacc_tu(vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vmacc_tu(vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vmacc_tu(vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vmacc_tu(vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vmacc_tu(vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vmacc_tu(vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vmacc_tu(vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vmacc_tu(vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vmacc_tu(vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vmacc_tu(vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vmacc_tu(vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vmacc_tu(vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vmacc_tu(vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vmacc_tu(vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vmacc_tu(vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-2.C
new file mode 100644
index 00000000000..97352d48659
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-2.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmacc_tu(vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vmacc_tu(vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vmacc_tu(vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vmacc_tu(vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vmacc_tu(vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vmacc_tu(vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vmacc_tu(vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vmacc_tu(vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vmacc_tu(vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vmacc_tu(vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vmacc_tu(vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vmacc_tu(vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vmacc_tu(vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vmacc_tu(vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vmacc_tu(vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vmacc_tu(vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vmacc_tu(vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vmacc_tu(vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vmacc_tu(vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vmacc_tu(vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vmacc_tu(vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vmacc_tu(vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vmacc_tu(vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vmacc_tu(vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vmacc_tu(vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vmacc_tu(vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vmacc_tu(vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vmacc_tu(vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vmacc_tu(vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vmacc_tu(vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vmacc_tu(vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vmacc_tu(vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vmacc_tu(vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vmacc_tu(vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vmacc_tu(vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vmacc_tu(vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vmacc_tu(vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vmacc_tu(vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vmacc_tu(vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vmacc_tu(vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vmacc_tu(vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vmacc_tu(vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vmacc_tu(vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vmacc_tu(vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-3.C
new file mode 100644
index 00000000000..06ecf47d189
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-3.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmacc_tu(vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vmacc_tu(vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vmacc_tu(vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vmacc_tu(vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vmacc_tu(vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vmacc_tu(vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vmacc_tu(vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vmacc_tu(vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vmacc_tu(vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vmacc_tu(vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vmacc_tu(vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vmacc_tu(vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vmacc_tu(vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vmacc_tu(vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vmacc_tu(vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vmacc_tu(vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vmacc_tu(vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vmacc_tu(vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vmacc_tu(vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vmacc_tu(vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vmacc_tu(vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vmacc_tu(vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vmacc_tu(vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vmacc_tu(vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vmacc_tu(vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vmacc_tu(vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vmacc_tu(vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vmacc_tu(vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vmacc_tu(vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vmacc_tu(vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vmacc_tu(vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vmacc_tu(vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vmacc_tu(vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vmacc_tu(vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vmacc_tu(vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vmacc_tu(vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vmacc_tu(vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vmacc_tu(vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vmacc_tu(vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vmacc_tu(vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vmacc_tu(vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vmacc_tu(vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vmacc_tu(vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vmacc_tu(vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tu(vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-1.C
new file mode 100644
index 00000000000..c7724ef1830
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-1.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmacc_tum(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmacc_tum(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmacc_tum(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vmacc_tum(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vmacc_tum(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vmacc_tum(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vmacc_tum(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmacc_tum(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmacc_tum(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vmacc_tum(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vmacc_tum(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vmacc_tum(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vmacc_tum(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmacc_tum(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vmacc_tum(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vmacc_tum(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vmacc_tum(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vmacc_tum(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vmacc_tum(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vmacc_tum(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vmacc_tum(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vmacc_tum(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmacc_tum(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmacc_tum(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmacc_tum(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vmacc_tum(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vmacc_tum(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vmacc_tum(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vmacc_tum(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vmacc_tum(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vmacc_tum(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vmacc_tum(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vmacc_tum(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vmacc_tum(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vmacc_tum(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vmacc_tum(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vmacc_tum(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vmacc_tum(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vmacc_tum(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vmacc_tum(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vmacc_tum(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vmacc_tum(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vmacc_tum(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vmacc_tum(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-2.C
new file mode 100644
index 00000000000..1e646aa314c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-2.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmacc_tum(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vmacc_tum(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vmacc_tum(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vmacc_tum(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vmacc_tum(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vmacc_tum(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vmacc_tum(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vmacc_tum(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vmacc_tum(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vmacc_tum(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vmacc_tum(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vmacc_tum(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vmacc_tum(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vmacc_tum(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vmacc_tum(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vmacc_tum(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vmacc_tum(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vmacc_tum(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vmacc_tum(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vmacc_tum(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vmacc_tum(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vmacc_tum(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vmacc_tum(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vmacc_tum(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vmacc_tum(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vmacc_tum(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vmacc_tum(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vmacc_tum(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vmacc_tum(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vmacc_tum(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vmacc_tum(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vmacc_tum(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vmacc_tum(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vmacc_tum(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vmacc_tum(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vmacc_tum(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vmacc_tum(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vmacc_tum(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vmacc_tum(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vmacc_tum(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vmacc_tum(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vmacc_tum(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vmacc_tum(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vmacc_tum(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-3.C
new file mode 100644
index 00000000000..efe01468bbf
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-3.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmacc_tum(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vmacc_tum(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vmacc_tum(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vmacc_tum(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vmacc_tum(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vmacc_tum(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vmacc_tum(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vmacc_tum(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vmacc_tum(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vmacc_tum(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vmacc_tum(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vmacc_tum(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vmacc_tum(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vmacc_tum(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vmacc_tum(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vmacc_tum(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vmacc_tum(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vmacc_tum(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vmacc_tum(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vmacc_tum(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vmacc_tum(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vmacc_tum(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vmacc_tum(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vmacc_tum(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vmacc_tum(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vmacc_tum(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vmacc_tum(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vmacc_tum(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vmacc_tum(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vmacc_tum(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vmacc_tum(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vmacc_tum(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vmacc_tum(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vmacc_tum(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vmacc_tum(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vmacc_tum(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vmacc_tum(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vmacc_tum(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vmacc_tum(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vmacc_tum(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vmacc_tum(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vmacc_tum(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vmacc_tum(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vmacc_tum(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tum(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-1.C
new file mode 100644
index 00000000000..099c15d4905
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-1.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmacc_tumu(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmacc_tumu(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmacc_tumu(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vmacc_tumu(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vmacc_tumu(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vmacc_tumu(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vmacc_tumu(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmacc_tumu(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmacc_tumu(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vmacc_tumu(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vmacc_tumu(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vmacc_tumu(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vmacc_tumu(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmacc_tumu(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vmacc_tumu(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vmacc_tumu(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vmacc_tumu(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vmacc_tumu(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vmacc_tumu(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vmacc_tumu(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vmacc_tumu(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vmacc_tumu(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vmacc_tumu(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vmacc_tumu(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vmacc_tumu(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vmacc_tumu(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vmacc_tumu(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vmacc_tumu(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vmacc_tumu(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vmacc_tumu(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vmacc_tumu(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vmacc_tumu(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vmacc_tumu(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vmacc_tumu(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vmacc_tumu(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vmacc_tumu(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vmacc_tumu(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vmacc_tumu(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vmacc_tumu(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vmacc_tumu(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vmacc_tumu(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vmacc_tumu(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vmacc_tumu(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vmacc_tumu(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-2.C
new file mode 100644
index 00000000000..3286ff83ae3
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-2.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmacc_tumu(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vmacc_tumu(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vmacc_tumu(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vmacc_tumu(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vmacc_tumu(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vmacc_tumu(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vmacc_tumu(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vmacc_tumu(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vmacc_tumu(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vmacc_tumu(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vmacc_tumu(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vmacc_tumu(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vmacc_tumu(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vmacc_tumu(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vmacc_tumu(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vmacc_tumu(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vmacc_tumu(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vmacc_tumu(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vmacc_tumu(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vmacc_tumu(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vmacc_tumu(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vmacc_tumu(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vmacc_tumu(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vmacc_tumu(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vmacc_tumu(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vmacc_tumu(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vmacc_tumu(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vmacc_tumu(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vmacc_tumu(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vmacc_tumu(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vmacc_tumu(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vmacc_tumu(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vmacc_tumu(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vmacc_tumu(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vmacc_tumu(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vmacc_tumu(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vmacc_tumu(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vmacc_tumu(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vmacc_tumu(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vmacc_tumu(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vmacc_tumu(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vmacc_tumu(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vmacc_tumu(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vmacc_tumu(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-3.C
new file mode 100644
index 00000000000..62f30f33f96
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-3.C
@@ -0,0 +1,292 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmacc_tumu(vbool64_t mask,vint8mf8_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vmacc_tumu(vbool32_t mask,vint8mf4_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vmacc_tumu(vbool16_t mask,vint8mf2_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vmacc_tumu(vbool8_t mask,vint8m1_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vmacc_tumu(vbool4_t mask,vint8m2_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vmacc_tumu(vbool2_t mask,vint8m4_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vmacc_tumu(vbool1_t mask,vint8m8_t vd,vint8m8_t vs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vmacc_tumu(vbool64_t mask,vint16mf4_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vmacc_tumu(vbool32_t mask,vint16mf2_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vmacc_tumu(vbool16_t mask,vint16m1_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vmacc_tumu(vbool8_t mask,vint16m2_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vmacc_tumu(vbool4_t mask,vint16m4_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vmacc_tumu(vbool2_t mask,vint16m8_t vd,vint16m8_t vs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vmacc_tumu(vbool64_t mask,vint32mf2_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vmacc_tumu(vbool32_t mask,vint32m1_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vmacc_tumu(vbool16_t mask,vint32m2_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vmacc_tumu(vbool8_t mask,vint32m4_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vmacc_tumu(vbool4_t mask,vint32m8_t vd,vint32m8_t vs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vmacc_tumu(vbool64_t mask,vint64m1_t vd,vint64m1_t vs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vmacc_tumu(vbool32_t mask,vint64m2_t vd,vint64m2_t vs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vmacc_tumu(vbool16_t mask,vint64m4_t vd,vint64m4_t vs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vmacc_tumu(vbool8_t mask,vint64m8_t vd,vint64m8_t vs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vmacc_tumu(vbool64_t mask,vuint8mf8_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vmacc_tumu(vbool32_t mask,vuint8mf4_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vmacc_tumu(vbool16_t mask,vuint8mf2_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vmacc_tumu(vbool8_t mask,vuint8m1_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vmacc_tumu(vbool4_t mask,vuint8m2_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vmacc_tumu(vbool2_t mask,vuint8m4_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vmacc_tumu(vbool1_t mask,vuint8m8_t vd,vuint8m8_t vs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vmacc_tumu(vbool64_t mask,vuint16mf4_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vmacc_tumu(vbool32_t mask,vuint16mf2_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vmacc_tumu(vbool16_t mask,vuint16m1_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vmacc_tumu(vbool8_t mask,vuint16m2_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vmacc_tumu(vbool4_t mask,vuint16m4_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vmacc_tumu(vbool2_t mask,vuint16m8_t vd,vuint16m8_t vs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vmacc_tumu(vbool64_t mask,vuint32mf2_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vmacc_tumu(vbool32_t mask,vuint32m1_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vmacc_tumu(vbool16_t mask,vuint32m2_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vmacc_tumu(vbool8_t mask,vuint32m4_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vmacc_tumu(vbool4_t mask,vuint32m8_t vd,vuint32m8_t vs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vmacc_tumu(vbool64_t mask,vuint64m1_t vd,vuint64m1_t vs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vmacc_tumu(vbool32_t mask,vuint64m2_t vd,vuint64m2_t vs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vmacc_tumu(vbool16_t mask,vuint64m4_t vd,vuint64m4_t vs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vmacc_tumu(vbool8_t mask,vuint64m8_t vd,vuint64m8_t vs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vmacc_tumu(mask,vd,vs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vma[c-d][c-d]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */