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Zhong Subject: [PATCH] RISC-V: Add vnmsac vx C api tests Date: Tue, 14 Feb 2023 21:57:12 +0800 Message-Id: <20230214135712.146813-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757815068353943552?= X-GMAIL-MSGID: =?utf-8?q?1757815068353943552?= From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-3.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-1.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-2.c: New test. * gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-3.c: New test. --- .../riscv/rvv/base/vnmsac_vx_m_rv32-1.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_m_rv32-2.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_m_rv32-3.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv32-1.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv32-2.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv32-3.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_rv32-1.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_rv32-2.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_rv32-3.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv32-1.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv32-2.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv32-3.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv32-1.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv32-2.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv32-3.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv32-1.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv32-2.c | 289 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv32-3.c | 289 ++++++++++++++++++ 18 files changed, 5202 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-1.c new file mode 100644 index 00000000000..563bf565197 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-1.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8_m(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8_m(mask,vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4_m(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4_m(mask,vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2_m(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2_m(mask,vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1_m(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1_m(mask,vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2_m(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2_m(mask,vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4_m(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4_m(mask,vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8_m(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8_m(mask,vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4_m(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4_m(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2_m(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2_m(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1_m(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1_m(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2_m(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2_m(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4_m(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4_m(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8_m(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8_m(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2_m(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2_m(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1_m(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1_m(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2_m(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2_m(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4_m(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4_m(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8_m(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8_m(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1_m(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1_m(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2_m(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2_m(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4_m(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4_m(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8_m(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8_m(mask,vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8_m(mask,vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4_m(mask,vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2_m(mask,vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1_m(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1_m(mask,vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2_m(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2_m(mask,vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4_m(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4_m(mask,vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8_m(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8_m(mask,vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4_m(mask,vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2_m(mask,vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1_m(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1_m(mask,vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2_m(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2_m(mask,vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4_m(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4_m(mask,vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8_m(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8_m(mask,vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2_m(mask,vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1_m(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1_m(mask,vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2_m(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2_m(mask,vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4_m(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4_m(mask,vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8_m(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8_m(mask,vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1_m(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1_m(mask,vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2_m(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2_m(mask,vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4_m(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4_m(mask,vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8_m(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8_m(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-2.c new file mode 100644 index 00000000000..45bbeb3e0f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-2.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8_m(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8_m(mask,vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4_m(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4_m(mask,vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2_m(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2_m(mask,vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1_m(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1_m(mask,vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2_m(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2_m(mask,vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4_m(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4_m(mask,vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8_m(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8_m(mask,vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4_m(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4_m(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2_m(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2_m(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1_m(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1_m(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2_m(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2_m(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4_m(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4_m(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8_m(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8_m(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2_m(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2_m(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1_m(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1_m(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2_m(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2_m(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4_m(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4_m(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8_m(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8_m(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1_m(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1_m(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2_m(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2_m(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4_m(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4_m(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8_m(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8_m(mask,vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8_m(mask,vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4_m(mask,vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2_m(mask,vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1_m(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1_m(mask,vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2_m(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2_m(mask,vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4_m(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4_m(mask,vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8_m(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8_m(mask,vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4_m(mask,vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2_m(mask,vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1_m(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1_m(mask,vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2_m(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2_m(mask,vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4_m(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4_m(mask,vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8_m(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8_m(mask,vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2_m(mask,vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1_m(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1_m(mask,vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2_m(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2_m(mask,vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4_m(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4_m(mask,vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8_m(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8_m(mask,vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1_m(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1_m(mask,vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2_m(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2_m(mask,vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4_m(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4_m(mask,vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8_m(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8_m(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-3.c new file mode 100644 index 00000000000..d12bdf7ac50 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-3.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8_m(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8_m(mask,vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4_m(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4_m(mask,vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2_m(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2_m(mask,vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1_m(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1_m(mask,vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2_m(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2_m(mask,vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4_m(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4_m(mask,vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8_m(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8_m(mask,vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4_m(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4_m(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2_m(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2_m(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1_m(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1_m(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2_m(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2_m(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4_m(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4_m(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8_m(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8_m(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2_m(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2_m(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1_m(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1_m(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2_m(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2_m(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4_m(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4_m(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8_m(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8_m(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1_m(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1_m(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2_m(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2_m(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4_m(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4_m(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8_m(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8_m(mask,vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8_m(mask,vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4_m(mask,vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2_m(mask,vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1_m(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1_m(mask,vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2_m(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2_m(mask,vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4_m(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4_m(mask,vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8_m(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8_m(mask,vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4_m(mask,vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2_m(mask,vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1_m(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1_m(mask,vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2_m(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2_m(mask,vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4_m(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4_m(mask,vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8_m(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8_m(mask,vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2_m(mask,vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1_m(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1_m(mask,vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2_m(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2_m(mask,vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4_m(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4_m(mask,vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8_m(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8_m(mask,vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1_m(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1_m(mask,vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2_m(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2_m(mask,vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4_m(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4_m(mask,vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8_m(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8_m(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-1.c new file mode 100644 index 00000000000..7ea5b449051 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-1.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8_mu(mask,vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4_mu(mask,vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2_mu(mask,vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1_mu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1_mu(mask,vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2_mu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2_mu(mask,vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4_mu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4_mu(mask,vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8_mu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8_mu(mask,vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4_mu(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1_mu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2_mu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4_mu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4_mu(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8_mu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8_mu(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1_mu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2_mu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4_mu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4_mu(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8_mu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1_mu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2_mu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4_mu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4_mu(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8_mu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1_mu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2_mu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4_mu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4_mu(mask,vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8_mu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1_mu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2_mu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4_mu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4_mu(mask,vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8_mu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1_mu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2_mu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4_mu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4_mu(mask,vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8_mu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8_mu(mask,vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1_mu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1_mu(mask,vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2_mu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2_mu(mask,vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4_mu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4_mu(mask,vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8_mu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8_mu(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-2.c new file mode 100644 index 00000000000..f2909341677 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-2.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8_mu(mask,vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4_mu(mask,vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2_mu(mask,vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1_mu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1_mu(mask,vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2_mu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2_mu(mask,vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4_mu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4_mu(mask,vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8_mu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8_mu(mask,vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4_mu(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2_mu(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1_mu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1_mu(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2_mu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2_mu(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4_mu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4_mu(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8_mu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8_mu(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2_mu(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1_mu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1_mu(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2_mu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2_mu(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4_mu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4_mu(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8_mu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8_mu(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1_mu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1_mu(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2_mu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2_mu(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4_mu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4_mu(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8_mu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8_mu(mask,vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8_mu(mask,vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4_mu(mask,vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2_mu(mask,vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1_mu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1_mu(mask,vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2_mu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2_mu(mask,vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4_mu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4_mu(mask,vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8_mu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8_mu(mask,vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4_mu(mask,vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2_mu(mask,vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1_mu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1_mu(mask,vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2_mu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2_mu(mask,vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4_mu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4_mu(mask,vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8_mu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8_mu(mask,vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2_mu(mask,vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1_mu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1_mu(mask,vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2_mu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2_mu(mask,vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4_mu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4_mu(mask,vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8_mu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8_mu(mask,vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1_mu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1_mu(mask,vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2_mu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2_mu(mask,vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4_mu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4_mu(mask,vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8_mu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8_mu(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-3.c new file mode 100644 index 00000000000..97a62e3051e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_mu_rv32-3.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8_mu(mask,vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4_mu(mask,vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2_mu(mask,vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1_mu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1_mu(mask,vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2_mu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2_mu(mask,vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4_mu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4_mu(mask,vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8_mu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8_mu(mask,vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4_mu(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2_mu(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1_mu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1_mu(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2_mu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2_mu(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4_mu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4_mu(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8_mu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8_mu(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2_mu(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1_mu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1_mu(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2_mu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2_mu(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4_mu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4_mu(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8_mu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8_mu(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1_mu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1_mu(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2_mu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2_mu(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4_mu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4_mu(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8_mu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8_mu(mask,vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8_mu(mask,vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4_mu(mask,vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2_mu(mask,vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1_mu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1_mu(mask,vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2_mu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2_mu(mask,vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4_mu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4_mu(mask,vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8_mu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8_mu(mask,vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4_mu(mask,vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2_mu(mask,vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1_mu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1_mu(mask,vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2_mu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2_mu(mask,vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4_mu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4_mu(mask,vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8_mu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8_mu(mask,vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2_mu(mask,vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1_mu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1_mu(mask,vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2_mu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2_mu(mask,vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4_mu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4_mu(mask,vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8_mu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8_mu(mask,vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1_mu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1_mu(mask,vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2_mu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2_mu(mask,vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4_mu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4_mu(mask,vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8_mu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8_mu(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv32-1.c new file mode 100644 index 00000000000..1f3d0e2e16d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv32-1.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8(vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4(vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2(vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1(vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2(vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4(vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8(vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4(vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2(vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1(vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2(vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4(vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8(vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2(vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1(vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2(vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4(vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8(vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1(vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2(vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4(vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8(vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8(vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4(vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2(vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1(vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2(vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4(vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8(vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4(vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2(vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1(vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2(vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4(vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8(vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2(vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1(vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2(vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4(vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8(vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1(vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2(vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4(vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8(vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv32-2.c new file mode 100644 index 00000000000..98e2b4fda2c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv32-2.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8(vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4(vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2(vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1(vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2(vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4(vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8(vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4(vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2(vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1(vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2(vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4(vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8(vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2(vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1(vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2(vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4(vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8(vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1(vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2(vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4(vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8(vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8(vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4(vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2(vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1(vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2(vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4(vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8(vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4(vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2(vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1(vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2(vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4(vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8(vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2(vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1(vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2(vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4(vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8(vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1(vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2(vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4(vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8(vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv32-3.c new file mode 100644 index 00000000000..211554e03e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_rv32-3.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8(vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4(vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2(vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1(vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2(vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4(vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8(vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4(vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2(vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1(vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2(vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4(vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8(vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2(vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1(vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2(vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4(vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8(vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1(vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2(vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4(vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8(vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8(vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4(vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2(vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1(vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2(vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4(vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8(vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4(vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2(vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1(vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2(vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4(vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8(vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2(vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1(vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2(vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4(vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8(vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1(vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2(vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4(vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8(vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-1.c new file mode 100644 index 00000000000..fa74c7fd90f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-1.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8_tu(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8_tu(vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4_tu(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4_tu(vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2_tu(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2_tu(vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1_tu(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1_tu(vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2_tu(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2_tu(vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4_tu(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4_tu(vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8_tu(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8_tu(vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4_tu(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4_tu(vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2_tu(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2_tu(vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1_tu(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1_tu(vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2_tu(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2_tu(vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4_tu(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4_tu(vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8_tu(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8_tu(vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2_tu(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2_tu(vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1_tu(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1_tu(vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2_tu(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2_tu(vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4_tu(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4_tu(vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8_tu(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8_tu(vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1_tu(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1_tu(vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2_tu(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2_tu(vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4_tu(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4_tu(vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8_tu(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8_tu(vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8_tu(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8_tu(vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4_tu(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4_tu(vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2_tu(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2_tu(vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1_tu(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1_tu(vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2_tu(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2_tu(vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4_tu(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4_tu(vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8_tu(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8_tu(vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4_tu(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4_tu(vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2_tu(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2_tu(vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1_tu(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1_tu(vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2_tu(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2_tu(vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4_tu(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4_tu(vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8_tu(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8_tu(vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2_tu(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2_tu(vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1_tu(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1_tu(vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2_tu(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2_tu(vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4_tu(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4_tu(vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8_tu(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8_tu(vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1_tu(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1_tu(vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2_tu(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2_tu(vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4_tu(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4_tu(vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8_tu(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8_tu(vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-2.c new file mode 100644 index 00000000000..74c8e0557f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-2.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8_tu(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8_tu(vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4_tu(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4_tu(vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2_tu(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2_tu(vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1_tu(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1_tu(vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2_tu(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2_tu(vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4_tu(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4_tu(vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8_tu(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8_tu(vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4_tu(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4_tu(vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2_tu(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2_tu(vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1_tu(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1_tu(vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2_tu(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2_tu(vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4_tu(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4_tu(vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8_tu(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8_tu(vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2_tu(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2_tu(vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1_tu(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1_tu(vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2_tu(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2_tu(vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4_tu(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4_tu(vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8_tu(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8_tu(vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1_tu(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1_tu(vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2_tu(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2_tu(vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4_tu(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4_tu(vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8_tu(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8_tu(vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8_tu(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8_tu(vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4_tu(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4_tu(vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2_tu(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2_tu(vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1_tu(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1_tu(vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2_tu(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2_tu(vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4_tu(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4_tu(vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8_tu(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8_tu(vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4_tu(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4_tu(vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2_tu(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2_tu(vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1_tu(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1_tu(vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2_tu(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2_tu(vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4_tu(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4_tu(vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8_tu(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8_tu(vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2_tu(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2_tu(vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1_tu(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1_tu(vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2_tu(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2_tu(vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4_tu(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4_tu(vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8_tu(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8_tu(vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1_tu(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1_tu(vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2_tu(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2_tu(vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4_tu(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4_tu(vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8_tu(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8_tu(vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-3.c new file mode 100644 index 00000000000..431847e9558 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tu_rv32-3.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8_tu(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8_tu(vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4_tu(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4_tu(vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2_tu(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2_tu(vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1_tu(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1_tu(vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2_tu(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2_tu(vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4_tu(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4_tu(vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8_tu(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8_tu(vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4_tu(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4_tu(vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2_tu(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2_tu(vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1_tu(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1_tu(vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2_tu(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2_tu(vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4_tu(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4_tu(vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8_tu(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8_tu(vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2_tu(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2_tu(vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1_tu(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1_tu(vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2_tu(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2_tu(vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4_tu(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4_tu(vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8_tu(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8_tu(vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1_tu(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1_tu(vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2_tu(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2_tu(vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4_tu(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4_tu(vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8_tu(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8_tu(vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8_tu(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8_tu(vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4_tu(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4_tu(vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2_tu(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2_tu(vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1_tu(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1_tu(vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2_tu(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2_tu(vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4_tu(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4_tu(vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8_tu(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8_tu(vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4_tu(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4_tu(vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2_tu(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2_tu(vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1_tu(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1_tu(vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2_tu(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2_tu(vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4_tu(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4_tu(vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8_tu(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8_tu(vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2_tu(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2_tu(vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1_tu(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1_tu(vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2_tu(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2_tu(vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4_tu(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4_tu(vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8_tu(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8_tu(vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1_tu(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1_tu(vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2_tu(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2_tu(vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4_tu(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4_tu(vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8_tu(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8_tu(vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-1.c new file mode 100644 index 00000000000..cc3be12b844 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-1.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8_tum(mask,vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4_tum(mask,vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2_tum(mask,vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1_tum(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1_tum(mask,vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2_tum(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2_tum(mask,vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4_tum(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4_tum(mask,vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8_tum(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8_tum(mask,vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4_tum(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1_tum(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2_tum(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4_tum(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4_tum(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8_tum(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8_tum(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1_tum(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2_tum(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4_tum(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4_tum(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8_tum(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1_tum(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2_tum(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4_tum(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4_tum(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8_tum(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1_tum(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2_tum(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4_tum(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4_tum(mask,vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8_tum(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1_tum(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2_tum(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4_tum(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4_tum(mask,vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8_tum(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1_tum(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2_tum(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4_tum(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4_tum(mask,vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8_tum(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8_tum(mask,vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1_tum(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1_tum(mask,vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2_tum(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2_tum(mask,vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4_tum(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4_tum(mask,vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8_tum(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8_tum(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-2.c new file mode 100644 index 00000000000..14314e58a32 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-2.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8_tum(mask,vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4_tum(mask,vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2_tum(mask,vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1_tum(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1_tum(mask,vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2_tum(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2_tum(mask,vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4_tum(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4_tum(mask,vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8_tum(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8_tum(mask,vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4_tum(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2_tum(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1_tum(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1_tum(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2_tum(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2_tum(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4_tum(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4_tum(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8_tum(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8_tum(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2_tum(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1_tum(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1_tum(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2_tum(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2_tum(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4_tum(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4_tum(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8_tum(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8_tum(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1_tum(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1_tum(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2_tum(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2_tum(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4_tum(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4_tum(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8_tum(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8_tum(mask,vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8_tum(mask,vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4_tum(mask,vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2_tum(mask,vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1_tum(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1_tum(mask,vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2_tum(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2_tum(mask,vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4_tum(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4_tum(mask,vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8_tum(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8_tum(mask,vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4_tum(mask,vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2_tum(mask,vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1_tum(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1_tum(mask,vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2_tum(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2_tum(mask,vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4_tum(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4_tum(mask,vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8_tum(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8_tum(mask,vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2_tum(mask,vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1_tum(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1_tum(mask,vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2_tum(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2_tum(mask,vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4_tum(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4_tum(mask,vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8_tum(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8_tum(mask,vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1_tum(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1_tum(mask,vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2_tum(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2_tum(mask,vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4_tum(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4_tum(mask,vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8_tum(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8_tum(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-3.c new file mode 100644 index 00000000000..0339bf7f6f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tum_rv32-3.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8_tum(mask,vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4_tum(mask,vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2_tum(mask,vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1_tum(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1_tum(mask,vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2_tum(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2_tum(mask,vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4_tum(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4_tum(mask,vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8_tum(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8_tum(mask,vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4_tum(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2_tum(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1_tum(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1_tum(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2_tum(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2_tum(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4_tum(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4_tum(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8_tum(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8_tum(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2_tum(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1_tum(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1_tum(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2_tum(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2_tum(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4_tum(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4_tum(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8_tum(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8_tum(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1_tum(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1_tum(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2_tum(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2_tum(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4_tum(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4_tum(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8_tum(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8_tum(mask,vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8_tum(mask,vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4_tum(mask,vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2_tum(mask,vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1_tum(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1_tum(mask,vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2_tum(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2_tum(mask,vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4_tum(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4_tum(mask,vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8_tum(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8_tum(mask,vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4_tum(mask,vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2_tum(mask,vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1_tum(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1_tum(mask,vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2_tum(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2_tum(mask,vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4_tum(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4_tum(mask,vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8_tum(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8_tum(mask,vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2_tum(mask,vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1_tum(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1_tum(mask,vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2_tum(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2_tum(mask,vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4_tum(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4_tum(mask,vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8_tum(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8_tum(mask,vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1_tum(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1_tum(mask,vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2_tum(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2_tum(mask,vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4_tum(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4_tum(mask,vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8_tum(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8_tum(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-1.c new file mode 100644 index 00000000000..d1ceb51f177 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-1.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1_tumu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2_tumu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4_tumu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8_tumu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1_tumu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2_tumu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4_tumu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8_tumu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1_tumu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2_tumu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4_tumu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8_tumu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1_tumu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2_tumu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4_tumu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8_tumu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4_tumu(mask,vd,rs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8_tumu(mask,vd,rs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-2.c new file mode 100644 index 00000000000..bfa5655ae99 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-2.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8_tumu(mask,vd,rs1,vs2,31); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4_tumu(mask,vd,rs1,vs2,31); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2_tumu(mask,vd,rs1,vs2,31); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1_tumu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1_tumu(mask,vd,rs1,vs2,31); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2_tumu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2_tumu(mask,vd,rs1,vs2,31); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4_tumu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4_tumu(mask,vd,rs1,vs2,31); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8_tumu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8_tumu(mask,vd,rs1,vs2,31); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4_tumu(mask,vd,rs1,vs2,31); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1_tumu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2_tumu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4_tumu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4_tumu(mask,vd,rs1,vs2,31); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8_tumu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8_tumu(mask,vd,rs1,vs2,31); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1_tumu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2_tumu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4_tumu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4_tumu(mask,vd,rs1,vs2,31); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8_tumu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1_tumu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2_tumu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4_tumu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4_tumu(mask,vd,rs1,vs2,31); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8_tumu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4_tumu(mask,vd,rs1,vs2,31); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4_tumu(mask,vd,rs1,vs2,31); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4_tumu(mask,vd,rs1,vs2,31); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8_tumu(mask,vd,rs1,vs2,31); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1_tumu(mask,vd,rs1,vs2,31); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2_tumu(mask,vd,rs1,vs2,31); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4_tumu(mask,vd,rs1,vs2,31); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8_tumu(mask,vd,rs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-3.c new file mode 100644 index 00000000000..a1b9a13b540 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-3.c @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnmsac_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf8_tumu(mask,vd,rs1,vs2,32); +} + + +vint8mf4_t test___riscv_vnmsac_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf4_tumu(mask,vd,rs1,vs2,32); +} + + +vint8mf2_t test___riscv_vnmsac_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8mf2_tumu(mask,vd,rs1,vs2,32); +} + + +vint8m1_t test___riscv_vnmsac_vx_i8m1_tumu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m1_tumu(mask,vd,rs1,vs2,32); +} + + +vint8m2_t test___riscv_vnmsac_vx_i8m2_tumu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m2_tumu(mask,vd,rs1,vs2,32); +} + + +vint8m4_t test___riscv_vnmsac_vx_i8m4_tumu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m4_tumu(mask,vd,rs1,vs2,32); +} + + +vint8m8_t test___riscv_vnmsac_vx_i8m8_tumu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i8m8_tumu(mask,vd,rs1,vs2,32); +} + + +vint16mf4_t test___riscv_vnmsac_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf4_tumu(mask,vd,rs1,vs2,32); +} + + +vint16mf2_t test___riscv_vnmsac_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16mf2_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m1_t test___riscv_vnmsac_vx_i16m1_tumu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m1_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m2_t test___riscv_vnmsac_vx_i16m2_tumu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m2_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m4_t test___riscv_vnmsac_vx_i16m4_tumu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m4_tumu(mask,vd,rs1,vs2,32); +} + + +vint16m8_t test___riscv_vnmsac_vx_i16m8_tumu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i16m8_tumu(mask,vd,rs1,vs2,32); +} + + +vint32mf2_t test___riscv_vnmsac_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32mf2_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m1_t test___riscv_vnmsac_vx_i32m1_tumu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m1_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m2_t test___riscv_vnmsac_vx_i32m2_tumu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m2_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m4_t test___riscv_vnmsac_vx_i32m4_tumu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m4_tumu(mask,vd,rs1,vs2,32); +} + + +vint32m8_t test___riscv_vnmsac_vx_i32m8_tumu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i32m8_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m1_t test___riscv_vnmsac_vx_i64m1_tumu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m1_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m2_t test___riscv_vnmsac_vx_i64m2_tumu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m2_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m4_t test___riscv_vnmsac_vx_i64m4_tumu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m4_tumu(mask,vd,rs1,vs2,32); +} + + +vint64m8_t test___riscv_vnmsac_vx_i64m8_tumu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_i64m8_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8mf8_t test___riscv_vnmsac_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf8_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8mf4_t test___riscv_vnmsac_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf4_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8mf2_t test___riscv_vnmsac_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8mf2_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8m1_t test___riscv_vnmsac_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m1_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8m2_t test___riscv_vnmsac_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m2_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8m4_t test___riscv_vnmsac_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m4_tumu(mask,vd,rs1,vs2,32); +} + + +vuint8m8_t test___riscv_vnmsac_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u8m8_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vnmsac_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf4_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vnmsac_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16mf2_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16m1_t test___riscv_vnmsac_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m1_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16m2_t test___riscv_vnmsac_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m2_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16m4_t test___riscv_vnmsac_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m4_tumu(mask,vd,rs1,vs2,32); +} + + +vuint16m8_t test___riscv_vnmsac_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u16m8_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vnmsac_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32mf2_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32m1_t test___riscv_vnmsac_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m1_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32m2_t test___riscv_vnmsac_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m2_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32m4_t test___riscv_vnmsac_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m4_tumu(mask,vd,rs1,vs2,32); +} + + +vuint32m8_t test___riscv_vnmsac_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u32m8_tumu(mask,vd,rs1,vs2,32); +} + + +vuint64m1_t test___riscv_vnmsac_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m1_tumu(mask,vd,rs1,vs2,32); +} + + +vuint64m2_t test___riscv_vnmsac_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m2_tumu(mask,vd,rs1,vs2,32); +} + + +vuint64m4_t test___riscv_vnmsac_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m4_tumu(mask,vd,rs1,vs2,32); +} + + +vuint64m8_t test___riscv_vnmsac_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl) +{ + return __riscv_vnmsac_vx_u64m8_tumu(mask,vd,rs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t} 2 } } */ +/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */